[PATCH] D90380: [llvm-exegesis] Do not try to assign random registers twice.

[Clement Courbet via Phabricator via llvm-commits]

courbet created this revision.
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Doing a random assignment assigns both tested (forward) and back-to-back
(backward) instructions.

When none of the tested instruction and back-to-back instruction have
implicit aliasing, we're currently trying to do a random register
asignment twice.

Fix this (see PR26418).


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D90380

Files:
  llvm/test/tools/llvm-exegesis/X86/latency-IN16rr.s
  llvm/tools/llvm-exegesis/lib/SerialSnippetGenerator.cpp


Index: llvm/tools/llvm-exegesis/lib/SerialSnippetGenerator.cpp
===================================================================
--- llvm/tools/llvm-exegesis/lib/SerialSnippetGenerator.cpp
+++ llvm/tools/llvm-exegesis/lib/SerialSnippetGenerator.cpp
@@ -140,7 +140,7 @@
       InstructionTemplate OtherIT(OtherInstr);
       if (!Forward.hasImplicitAliasing())
         setRandomAliasing(Forward, ThisIT, OtherIT);
-      if (!Back.hasImplicitAliasing())
+      else if (!Back.hasImplicitAliasing())
         setRandomAliasing(Back, OtherIT, ThisIT);
       CodeTemplate CT;
       CT.Execution = ExecutionModeBit;
Index: llvm/test/tools/llvm-exegesis/X86/latency-IN16rr.s
===================================================================
--- /dev/null
+++ llvm/test/tools/llvm-exegesis/X86/latency-IN16rr.s
@@ -0,0 +1,12 @@
+# RUN: llvm-exegesis -mode=latency -opcode-name=IN16rr -repetition-mode=duplicate | FileCheck %s
+
+CHECK:      ---
+CHECK-NEXT: mode: latency
+CHECK-NEXT: key:
+CHECK-NEXT:   instructions:
+CHECK-NEXT:     - 'IN16rr'
+CHECK-NEXT:     - {{.*}}
+CHECK-NEXT: config: ''
+CHECK-NEXT: register_initial_values:
+CHECK-DAG: - '[[REG1:[A-Z0-9]+]]=0x0'
+CHECK-LAST: ...


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