[PATCH] D90347: [AMDGPU] Add Reset function to GCNHazardRecognizer
Austin Kerbow via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Oct 28 16:33:26 PDT 2020
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGde518673436e: [AMDGPU] Add Reset function to GCNHazardRecognizer (authored by kerbowa).
Changed prior to commit:
https://reviews.llvm.org/D90347?vs=301453&id=301472#toc
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D90347/new/
https://reviews.llvm.org/D90347
Files:
llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
llvm/lib/Target/AMDGPU/GCNHazardRecognizer.h
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mov.dpp.ll
llvm/test/CodeGen/AMDGPU/post-ra-sched-reset.mir
Index: llvm/test/CodeGen/AMDGPU/post-ra-sched-reset.mir
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AMDGPU/post-ra-sched-reset.mir
@@ -0,0 +1,22 @@
+# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=post-RA-sched -verify-machineinstrs -debug-only=post-RA-sched -o - %s 2>&1 | FileCheck %s
+
+# REQUIRES: asserts
+
+# CHECK-NOT: Stall in cycle
+---
+name: hazard_rec_reset
+tracksRegLiveness: true
+body: |
+ bb.0:
+ successors: %bb.1
+
+ $m0 = S_MOV_B32 0
+
+ bb.1:
+ liveins: $vgpr4
+
+ S_SETREG_IMM32_B32 0, 1, implicit-def $mode, implicit $mode
+ $vgpr0 = V_INTERP_P1_F32 killed $vgpr4, 0, 0, implicit $mode, implicit $m0, implicit $exec
+ S_ENDPGM 0
+
+...
Index: llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mov.dpp.ll
===================================================================
--- llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mov.dpp.ll
+++ llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mov.dpp.ll
@@ -34,12 +34,11 @@
; VI-LABEL: {{^}}dpp_first_in_bb:
; VI: ; %endif
-; PREGFX10-OPT: s_mov_b32
-; PREGFX10-OPT: s_mov_b32
; PREGFX10-NOOPT: s_waitcnt
; PREGFX10-NOOPT: v_mov_b32_e32
; VI: v_mov_b32_dpp [[VGPR0:v[0-9]+]], v{{[0-9]+}} quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:0
-; PREGFX10: s_nop 1
+; PREGFX10-OPT: s_mov_b32
+; PREGFX10-OPT: s_mov_b32
; VI: v_mov_b32_dpp [[VGPR1:v[0-9]+]], [[VGPR0]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:0
; PREGFX10: s_nop 1
; VI: v_mov_b32_dpp v{{[0-9]+}}, [[VGPR1]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:0
Index: llvm/lib/Target/AMDGPU/GCNHazardRecognizer.h
===================================================================
--- llvm/lib/Target/AMDGPU/GCNHazardRecognizer.h
+++ llvm/lib/Target/AMDGPU/GCNHazardRecognizer.h
@@ -109,6 +109,7 @@
void AdvanceCycle() override;
void RecedeCycle() override;
bool ShouldPreferAnother(SUnit *SU) override;
+ void Reset() override;
};
} // end namespace llvm
Index: llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
+++ llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
@@ -50,6 +50,10 @@
TSchedModel.init(&ST);
}
+void GCNHazardRecognizer::Reset() {
+ EmittedInstrs.clear();
+}
+
void GCNHazardRecognizer::EmitInstruction(SUnit *SU) {
EmitInstruction(SU->getInstr());
}
-------------- next part --------------
A non-text attachment was scrubbed...
Name: D90347.301472.patch
Type: text/x-patch
Size: 2446 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20201028/bcb77739/attachment.bin>
More information about the llvm-commits
mailing list