[PATCH] D90307: [AMDGPU] Fix double space in disassembly of ds_gws_sema_* with gds
Jay Foad via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Oct 28 07:55:42 PDT 2020
foad updated this revision to Diff 301286.
foad added a comment.
Rebase after adding -strict-whitespace to the tests.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D90307/new/
https://reviews.llvm.org/D90307
Files:
llvm/lib/Target/AMDGPU/DSInstructions.td
llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
llvm/test/MC/Disassembler/AMDGPU/gfx10_dasm_all.txt
Index: llvm/test/MC/Disassembler/AMDGPU/gfx10_dasm_all.txt
===================================================================
--- llvm/test/MC/Disassembler/AMDGPU/gfx10_dasm_all.txt
+++ llvm/test/MC/Disassembler/AMDGPU/gfx10_dasm_all.txt
@@ -3623,7 +3623,7 @@
# GFX10: ds_gws_sema_br v255 offset:65535 gds ; encoding: [0xff,0xff,0x6e,0xd8,0xff,0x00,0x00,0x00]
0xff,0xff,0x6e,0xd8,0xff,0x00,0x00,0x00
-# GFX10: ds_gws_sema_p gds ; encoding: [0x00,0x00,0x72,0xd8,0x00,0x00,0x00,0x00]
+# GFX10: ds_gws_sema_p gds ; encoding: [0x00,0x00,0x72,0xd8,0x00,0x00,0x00,0x00]
0x00,0x00,0x72,0xd8,0x00,0x00,0x00,0x00
# GFX10: ds_gws_sema_p offset:4660 gds ; encoding: [0x34,0x12,0x72,0xd8,0x00,0x00,0x00,0x00]
@@ -3632,7 +3632,7 @@
# GFX10: ds_gws_sema_p offset:65535 gds ; encoding: [0xff,0xff,0x72,0xd8,0x00,0x00,0x00,0x00]
0xff,0xff,0x72,0xd8,0x00,0x00,0x00,0x00
-# GFX10: ds_gws_sema_release_all gds ; encoding: [0x00,0x00,0x62,0xd8,0x00,0x00,0x00,0x00]
+# GFX10: ds_gws_sema_release_all gds ; encoding: [0x00,0x00,0x62,0xd8,0x00,0x00,0x00,0x00]
0x00,0x00,0x62,0xd8,0x00,0x00,0x00,0x00
# GFX10: ds_gws_sema_release_all offset:4660 gds ; encoding: [0x34,0x12,0x62,0xd8,0x00,0x00,0x00,0x00]
@@ -3641,7 +3641,7 @@
# GFX10: ds_gws_sema_release_all offset:65535 gds ; encoding: [0xff,0xff,0x62,0xd8,0x00,0x00,0x00,0x00]
0xff,0xff,0x62,0xd8,0x00,0x00,0x00,0x00
-# GFX10: ds_gws_sema_v gds ; encoding: [0x00,0x00,0x6a,0xd8,0x00,0x00,0x00,0x00]
+# GFX10: ds_gws_sema_v gds ; encoding: [0x00,0x00,0x6a,0xd8,0x00,0x00,0x00,0x00]
0x00,0x00,0x6a,0xd8,0x00,0x00,0x00,0x00
# GFX10: ds_gws_sema_v offset:4660 gds ; encoding: [0x34,0x12,0x6a,0xd8,0x00,0x00,0x00,0x00]
Index: llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
+++ llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
@@ -138,6 +138,8 @@
if (Imm != 0) {
O << ((OpNo == 0)? "offset:" : " offset:");
printU16ImmDecOperand(MI, OpNo, O);
+ if (OpNo == 0)
+ O << " ";
}
}
Index: llvm/lib/Target/AMDGPU/DSInstructions.td
===================================================================
--- llvm/lib/Target/AMDGPU/DSInstructions.td
+++ llvm/lib/Target/AMDGPU/DSInstructions.td
@@ -330,7 +330,7 @@
class DS_GWS_0D <string opName>
: DS_GWS<opName,
- (ins offset:$offset, gds:$gds), "$offset gds"> {
+ (ins offset:$offset, gds:$gds), "${offset}gds"> {
let hasSideEffects = 1;
}
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