[PATCH] D90296: [AMDGPU] Allow some modifiers on VOP3B instructions

Wed Oct 28 06:56:54 PDT 2020

arsenm added inline comments.

================
Comment at: llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp:3312-3317
+  case V_DIV_SCALE_F32_gfx6_gfx7:
+  case V_DIV_SCALE_F32_vi:
+  case V_DIV_SCALE_F32_gfx10:
+  case V_DIV_SCALE_F64_gfx6_gfx7:
+  case V_DIV_SCALE_F64_vi:
+  case V_DIV_SCALE_F64_gfx10:
----------------
foad wrote:
> arsenm wrote:
> > foad wrote:
> > > Is there a better way than listing all the real opcodes for all architectures?
> > Probably not right now, other than burning a bit for IsDivScale which is probably not worth it.
> Could we get TableGen to emit a real-to-pseudo opcode mapping table, like it generates pseudo-to-real tables?
I've been thinking of trying an alternative strategy where we emit entirely separate instruction tables per subtarget

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D90296/new/

https://reviews.llvm.org/D90296