[llvm] ecd4f3f - [AArch64] Additional Interleaving Access test. NFC

David Green via llvm-commits llvm-commits at lists.llvm.org
Wed Oct 28 01:00:20 PDT 2020


Author: David Green
Date: 2020-10-28T08:00:05Z
New Revision: ecd4f3fccb04f1968e6ddb0171221a7c28346d4b

URL: https://github.com/llvm/llvm-project/commit/ecd4f3fccb04f1968e6ddb0171221a7c28346d4b
DIFF: https://github.com/llvm/llvm-project/commit/ecd4f3fccb04f1968e6ddb0171221a7c28346d4b.diff

LOG: [AArch64] Additional Interleaving Access test. NFC

Added: 
    llvm/test/Transforms/InterleavedAccess/AArch64/binopshuffles.ll

Modified: 
    

Removed: 
    


################################################################################
diff  --git a/llvm/test/Transforms/InterleavedAccess/AArch64/binopshuffles.ll b/llvm/test/Transforms/InterleavedAccess/AArch64/binopshuffles.ll
new file mode 100644
index 000000000000..a1e1b4dbe748
--- /dev/null
+++ b/llvm/test/Transforms/InterleavedAccess/AArch64/binopshuffles.ll
@@ -0,0 +1,132 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -interleaved-access -S | FileCheck %s
+
+target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
+target triple = "aarch64--linux-gnu"
+
+define <4 x float> @vld2(<8 x float>* %pSrc) {
+; CHECK-LABEL: @vld2(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[WIDE_VEC:%.*]] = load <8 x float>, <8 x float>* [[PSRC:%.*]], align 4
+; CHECK-NEXT:    [[L2:%.*]] = fmul fast <8 x float> [[WIDE_VEC]], [[WIDE_VEC]]
+; CHECK-NEXT:    [[L3:%.*]] = shufflevector <8 x float> [[L2]], <8 x float> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
+; CHECK-NEXT:    [[L4:%.*]] = fmul fast <8 x float> [[WIDE_VEC]], [[WIDE_VEC]]
+; CHECK-NEXT:    [[L5:%.*]] = shufflevector <8 x float> [[L4]], <8 x float> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
+; CHECK-NEXT:    [[L6:%.*]] = fadd fast <4 x float> [[L5]], [[L3]]
+; CHECK-NEXT:    ret <4 x float> [[L6]]
+;
+entry:
+  %wide.vec = load <8 x float>, <8 x float>* %pSrc, align 4
+  %l2 = fmul fast <8 x float> %wide.vec, %wide.vec
+  %l3 = shufflevector <8 x float> %l2, <8 x float> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
+  %l4 = fmul fast <8 x float> %wide.vec, %wide.vec
+  %l5 = shufflevector <8 x float> %l4, <8 x float> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
+  %l6 = fadd fast <4 x float> %l5, %l3
+  ret <4 x float> %l6
+}
+
+define <4 x float> @vld3(<12 x float>* %pSrc) {
+; CHECK-LABEL: @vld3(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[WIDE_VEC:%.*]] = load <12 x float>, <12 x float>* [[PSRC:%.*]], align 4
+; CHECK-NEXT:    [[L2:%.*]] = fmul fast <12 x float> [[WIDE_VEC]], [[WIDE_VEC]]
+; CHECK-NEXT:    [[L3:%.*]] = shufflevector <12 x float> [[L2]], <12 x float> undef, <4 x i32> <i32 0, i32 3, i32 6, i32 9>
+; CHECK-NEXT:    [[L4:%.*]] = fmul fast <12 x float> [[WIDE_VEC]], [[WIDE_VEC]]
+; CHECK-NEXT:    [[L5:%.*]] = shufflevector <12 x float> [[L4]], <12 x float> undef, <4 x i32> <i32 1, i32 4, i32 7, i32 10>
+; CHECK-NEXT:    [[L6:%.*]] = fadd fast <4 x float> [[L5]], [[L3]]
+; CHECK-NEXT:    [[L7:%.*]] = fmul fast <12 x float> [[WIDE_VEC]], [[WIDE_VEC]]
+; CHECK-NEXT:    [[L8:%.*]] = shufflevector <12 x float> [[L7]], <12 x float> undef, <4 x i32> <i32 2, i32 5, i32 8, i32 11>
+; CHECK-NEXT:    [[L9:%.*]] = fadd fast <4 x float> [[L6]], [[L8]]
+; CHECK-NEXT:    ret <4 x float> [[L9]]
+;
+entry:
+  %wide.vec = load <12 x float>, <12 x float>* %pSrc, align 4
+  %l2 = fmul fast <12 x float> %wide.vec, %wide.vec
+  %l3 = shufflevector <12 x float> %l2, <12 x float> undef, <4 x i32> <i32 0, i32 3, i32 6, i32 9>
+  %l4 = fmul fast <12 x float> %wide.vec, %wide.vec
+  %l5 = shufflevector <12 x float> %l4, <12 x float> undef, <4 x i32> <i32 1, i32 4, i32 7, i32 10>
+  %l6 = fadd fast <4 x float> %l5, %l3
+  %l7 = fmul fast <12 x float> %wide.vec, %wide.vec
+  %l8 = shufflevector <12 x float> %l7, <12 x float> undef, <4 x i32> <i32 2, i32 5, i32 8, i32 11>
+  %l9 = fadd fast <4 x float> %l6, %l8
+  ret <4 x float> %l9
+}
+
+define <4 x float> @vld4(<16 x float>* %pSrc) {
+; CHECK-LABEL: @vld4(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[WIDE_VEC:%.*]] = load <16 x float>, <16 x float>* [[PSRC:%.*]], align 4
+; CHECK-NEXT:    [[L3:%.*]] = fmul fast <16 x float> [[WIDE_VEC]], [[WIDE_VEC]]
+; CHECK-NEXT:    [[L4:%.*]] = shufflevector <16 x float> [[L3]], <16 x float> undef, <4 x i32> <i32 0, i32 4, i32 8, i32 12>
+; CHECK-NEXT:    [[L5:%.*]] = fmul fast <16 x float> [[WIDE_VEC]], [[WIDE_VEC]]
+; CHECK-NEXT:    [[L6:%.*]] = shufflevector <16 x float> [[L5]], <16 x float> undef, <4 x i32> <i32 1, i32 5, i32 9, i32 13>
+; CHECK-NEXT:    [[L7:%.*]] = fadd fast <4 x float> [[L6]], [[L4]]
+; CHECK-NEXT:    [[L8:%.*]] = fmul fast <16 x float> [[WIDE_VEC]], [[WIDE_VEC]]
+; CHECK-NEXT:    [[L9:%.*]] = shufflevector <16 x float> [[L8]], <16 x float> undef, <4 x i32> <i32 2, i32 6, i32 10, i32 14>
+; CHECK-NEXT:    [[L10:%.*]] = fmul fast <16 x float> [[WIDE_VEC]], [[WIDE_VEC]]
+; CHECK-NEXT:    [[L11:%.*]] = shufflevector <16 x float> [[L10]], <16 x float> undef, <4 x i32> <i32 3, i32 7, i32 11, i32 15>
+; CHECK-NEXT:    [[L12:%.*]] = fadd fast <4 x float> [[L11]], [[L9]]
+; CHECK-NEXT:    ret <4 x float> [[L12]]
+;
+entry:
+  %wide.vec = load <16 x float>, <16 x float>* %pSrc, align 4
+  %l3 = fmul fast <16 x float> %wide.vec, %wide.vec
+  %l4 = shufflevector <16 x float> %l3, <16 x float> undef, <4 x i32> <i32 0, i32 4, i32 8, i32 12>
+  %l5 = fmul fast <16 x float> %wide.vec, %wide.vec
+  %l6 = shufflevector <16 x float> %l5, <16 x float> undef, <4 x i32> <i32 1, i32 5, i32 9, i32 13>
+  %l7 = fadd fast <4 x float> %l6, %l4
+  %l8 = fmul fast <16 x float> %wide.vec, %wide.vec
+  %l9 = shufflevector <16 x float> %l8, <16 x float> undef, <4 x i32> <i32 2, i32 6, i32 10, i32 14>
+  %l10 = fmul fast <16 x float> %wide.vec, %wide.vec
+  %l11 = shufflevector <16 x float> %l10, <16 x float> undef, <4 x i32> <i32 3, i32 7, i32 11, i32 15>
+  %l12 = fadd fast <4 x float> %l11, %l9
+  ret <4 x float> %l12
+}
+
+define <4 x float> @twosrc(<8 x float>* %pSrc1, <8 x float>* %pSrc2) {
+; CHECK-LABEL: @twosrc(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[WIDE_VEC:%.*]] = load <8 x float>, <8 x float>* [[PSRC1:%.*]], align 4
+; CHECK-NEXT:    [[WIDE_VEC26:%.*]] = load <8 x float>, <8 x float>* [[PSRC2:%.*]], align 4
+; CHECK-NEXT:    [[L4:%.*]] = fmul fast <8 x float> [[WIDE_VEC26]], [[WIDE_VEC]]
+; CHECK-NEXT:    [[L5:%.*]] = shufflevector <8 x float> [[L4]], <8 x float> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
+; CHECK-NEXT:    [[L6:%.*]] = fmul fast <8 x float> [[WIDE_VEC26]], [[WIDE_VEC]]
+; CHECK-NEXT:    [[L7:%.*]] = shufflevector <8 x float> [[L6]], <8 x float> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
+; CHECK-NEXT:    [[L8:%.*]] = fadd fast <4 x float> [[L7]], [[L5]]
+; CHECK-NEXT:    ret <4 x float> [[L8]]
+;
+entry:
+  %wide.vec = load <8 x float>, <8 x float>* %pSrc1, align 4
+  %wide.vec26 = load <8 x float>, <8 x float>* %pSrc2, align 4
+  %l4 = fmul fast <8 x float> %wide.vec26, %wide.vec
+  %l5 = shufflevector <8 x float> %l4, <8 x float> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
+  %l6 = fmul fast <8 x float> %wide.vec26, %wide.vec
+  %l7 = shufflevector <8 x float> %l6, <8 x float> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
+  %l8 = fadd fast <4 x float> %l7, %l5
+  ret <4 x float> %l8
+}
+
+define <4 x float> @twosrc2(<8 x float>* %pSrc1, <8 x float>* %pSrc2) {
+; CHECK-LABEL: @twosrc2(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[WIDE_VEC:%.*]] = load <8 x float>, <8 x float>* [[PSRC1:%.*]], align 4
+; CHECK-NEXT:    [[WIDE_VEC26:%.*]] = load <8 x float>, <8 x float>* [[PSRC2:%.*]], align 4
+; CHECK-NEXT:    [[L4:%.*]] = fmul fast <8 x float> [[WIDE_VEC26]], [[WIDE_VEC]]
+; CHECK-NEXT:    [[L5:%.*]] = shufflevector <8 x float> [[L4]], <8 x float> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
+; CHECK-NEXT:    [[S1:%.*]] = shufflevector <8 x float> [[WIDE_VEC26]], <8 x float> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
+; CHECK-NEXT:    [[S2:%.*]] = shufflevector <8 x float> [[WIDE_VEC]], <8 x float> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
+; CHECK-NEXT:    [[L6:%.*]] = fmul fast <4 x float> [[S1]], [[S2]]
+; CHECK-NEXT:    [[L8:%.*]] = fadd fast <4 x float> [[L6]], [[L5]]
+; CHECK-NEXT:    ret <4 x float> [[L8]]
+;
+entry:
+  %wide.vec = load <8 x float>, <8 x float>* %pSrc1, align 4
+  %wide.vec26 = load <8 x float>, <8 x float>* %pSrc2, align 4
+  %l4 = fmul fast <8 x float> %wide.vec26, %wide.vec
+  %l5 = shufflevector <8 x float> %l4, <8 x float> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
+  %s1 = shufflevector <8 x float> %wide.vec26, <8 x float> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
+  %s2 = shufflevector <8 x float> %wide.vec, <8 x float> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
+  %l6 = fmul fast <4 x float> %s1, %s2
+  %l8 = fadd fast <4 x float> %l6, %l5
+  ret <4 x float> %l8
+}


        


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