[PATCH] D90247: [AArch64] Add legalizations for VECREDUCE_SEQ_FADD

[Sanjay Patel via Phabricator via llvm-commits]

spatel added a comment.

In D90247#2357013 <https://reviews.llvm.org/D90247#2357013>, @nikic wrote:

> Looking at https://github.com/llvm/llvm-project/blob/5a3ef55a524bf9e072d98286e5febdb218b1fc72/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp#L7477-L7480, shouldn't this just be a matter of using `-0.0` as the neutral element instead? If `0.0` is not actually neutral here, then this is not just suboptimal, it's incorrect. (We should fix this for the non-sequential case as well.)

Agree - looks like the -0.0 was missed in D58015 <https://reviews.llvm.org/D58015>. Note that we have semi-redundant logic for this sort of thing in IR with ConstantExpr::getBinOpIdentity(), so we should confirm that everything is lined up and/or try to consolidate code.


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https://reviews.llvm.org/D90247