[llvm] 4b1ea84 - [AMDGPU] Fix check prefix for VOP3 VI disassembler tests
Jay Foad via llvm-commits
llvm-commits at lists.llvm.org
Tue Oct 27 11:45:11 PDT 2020
Author: Jay Foad
Date: 2020-10-27T18:43:25Z
New Revision: 4b1ea84a1d04820248a4247cb1efa54c18765a6a
URL: https://github.com/llvm/llvm-project/commit/4b1ea84a1d04820248a4247cb1efa54c18765a6a
DIFF: https://github.com/llvm/llvm-project/commit/4b1ea84a1d04820248a4247cb1efa54c18765a6a.diff
LOG: [AMDGPU] Fix check prefix for VOP3 VI disassembler tests
Also, following D81841, don't try to encode f16 literals in i16/u16
instructions.
Differential Revision: https://reviews.llvm.org/D90242
Added:
Modified:
llvm/test/MC/Disassembler/AMDGPU/vop3_gfx9.txt
llvm/test/MC/Disassembler/AMDGPU/vop3_vi.txt
Removed:
################################################################################
diff --git a/llvm/test/MC/Disassembler/AMDGPU/vop3_gfx9.txt b/llvm/test/MC/Disassembler/AMDGPU/vop3_gfx9.txt
index 4f9e4b7fd7c7..fbbd8ae86412 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/vop3_gfx9.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/vop3_gfx9.txt
@@ -114,8 +114,8 @@
# GFX9: v_mad_i16 v5, v1, -1, v3 ; encoding: [0x05,0x00,0x05,0xd2,0x01,0x83,0x0d,0x04]
0x05,0x00,0x05,0xd2,0x01,0x83,0x0d,0x04
-# GFX9: v_mad_i16 v5, v1, v2, 0xc400 ; encoding: [0x05,0x00,0x05,0xd2,0x01,0x05,0xfe,0x03]
-0x05,0x00,0x05,0xd2,0x01,0x05,0xde,0x03
+# GFX9: v_mad_i16 v5, v1, v2, 63 ; encoding: [0x05,0x00,0x05,0xd2,0x01,0x05,0xfe,0x02]
+0x05,0x00,0x05,0xd2,0x01,0x05,0xfe,0x02
# GFX9: v_mad_i16 v5, v1, v2, v3 op_sel:[0,0,0,1] ; encoding: [0x05,0x40,0x05,0xd2,0x01,0x05,0x0e,0x04]
0x05,0x40,0x05,0xd2,0x01,0x05,0x0e,0x04
@@ -174,8 +174,8 @@
# GFX9: v_mad_u16 v5, v1, -1, v3 ; encoding: [0x05,0x00,0x04,0xd2,0x01,0x83,0x0d,0x04]
0x05,0x00,0x04,0xd2,0x01,0x83,0x0d,0x04
-# GFX9: v_mad_u16 v5, v1, v2, 0xc400 ; encoding: [0x05,0x00,0x04,0xd2,0x01,0x05,0xfe,0x03]
-0x05,0x00,0x04,0xd2,0x01,0x05,0xde,0x03
+# GFX9: v_mad_u16 v5, v1, v2, 63 ; encoding: [0x05,0x00,0x04,0xd2,0x01,0x05,0xfe,0x02]
+0x05,0x00,0x04,0xd2,0x01,0x05,0xfe,0x02
# GFX9: v_mad_u16 v5, v1, v2, v3 op_sel:[1,0,0,0] ; encoding: [0x05,0x08,0x04,0xd2,0x01,0x05,0x0e,0x04]
0x05,0x08,0x04,0xd2,0x01,0x05,0x0e,0x04
diff --git a/llvm/test/MC/Disassembler/AMDGPU/vop3_vi.txt b/llvm/test/MC/Disassembler/AMDGPU/vop3_vi.txt
index b4c2f183ca13..cd9a65cc13e8 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/vop3_vi.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/vop3_vi.txt
@@ -261,59 +261,59 @@
# VI: v_fma_f16 v5, v1, v2, v3 clamp ; encoding: [0x05,0x80,0xee,0xd1,0x01,0x05,0x0e,0x04]
0x05,0x80,0xee,0xd1,0x01,0x05,0x0e,0x04
-# CHECK: v_div_fixup_f16 v5, 0.5, v2, v3 ; encoding: [0x05,0x00,0xef,0xd1,0xf0,0x04,0x0e,0x04]
+# VI: v_div_fixup_f16 v5, 0.5, v2, v3 ; encoding: [0x05,0x00,0xef,0xd1,0xf0,0x04,0x0e,0x04]
0x05,0x00,0xef,0xd1,0xf0,0x04,0x0e,0x04
-# CHECK: v_div_fixup_f16 v5, v1, 0.5, v3 ; encoding: [0x05,0x00,0xef,0xd1,0x01,0xe1,0x0d,0x04]
+# VI: v_div_fixup_f16 v5, v1, 0.5, v3 ; encoding: [0x05,0x00,0xef,0xd1,0x01,0xe1,0x0d,0x04]
0x05,0x00,0xef,0xd1,0x01,0xe1,0x0d,0x04
-# CHECK: v_div_fixup_f16 v5, v1, v2, 0.5 ; encoding: [0x05,0x00,0xef,0xd1,0x01,0x05,0xc2,0x03]
+# VI: v_div_fixup_f16 v5, v1, v2, 0.5 ; encoding: [0x05,0x00,0xef,0xd1,0x01,0x05,0xc2,0x03]
0x05,0x00,0xef,0xd1,0x01,0x05,0xc2,0x03
-# CHECK: v_div_fixup_f16 v5, -v1, -v2, -v3 ; encoding: [0x05,0x00,0xef,0xd1,0x01,0x05,0x0e,0xe4]
+# VI: v_div_fixup_f16 v5, -v1, -v2, -v3 ; encoding: [0x05,0x00,0xef,0xd1,0x01,0x05,0x0e,0xe4]
0x05,0x00,0xef,0xd1,0x01,0x05,0x0e,0xe4
-# CHECK: v_div_fixup_f16 v5, |v1|, |v2|, |v3| ; encoding: [0x05,0x07,0xef,0xd1,0x01,0x05,0x0e,0x04]
+# VI: v_div_fixup_f16 v5, |v1|, |v2|, |v3| ; encoding: [0x05,0x07,0xef,0xd1,0x01,0x05,0x0e,0x04]
0x05,0x07,0xef,0xd1,0x01,0x05,0x0e,0x04
-# CHECK: v_div_fixup_f16 v5, v1, v2, v3 clamp ; encoding: [0x05,0x80,0xef,0xd1,0x01,0x05,0x0e,0x04]
+# VI: v_div_fixup_f16 v5, v1, v2, v3 clamp ; encoding: [0x05,0x80,0xef,0xd1,0x01,0x05,0x0e,0x04]
0x05,0x80,0xef,0xd1,0x01,0x05,0x0e,0x04
-# CHECK: v_mad_f16 v5, 0.5, v2, v3 ; encoding: [0x05,0x00,0xea,0xd1,0xf0,0x04,0x0e,0x04]
+# VI: v_mad_f16 v5, 0.5, v2, v3 ; encoding: [0x05,0x00,0xea,0xd1,0xf0,0x04,0x0e,0x04]
0x05,0x00,0xea,0xd1,0xf0,0x04,0x0e,0x04
-# CHECK: v_mad_f16 v5, v1, 0.5, v3 ; encoding: [0x05,0x00,0xea,0xd1,0x01,0xe1,0x0d,0x04]
+# VI: v_mad_f16 v5, v1, 0.5, v3 ; encoding: [0x05,0x00,0xea,0xd1,0x01,0xe1,0x0d,0x04]
0x05,0x00,0xea,0xd1,0x01,0xe1,0x0d,0x04
-# CHECK: v_mad_f16 v5, v1, v2, 0.5 ; encoding: [0x05,0x00,0xea,0xd1,0x01,0x05,0xc2,0x03]
+# VI: v_mad_f16 v5, v1, v2, 0.5 ; encoding: [0x05,0x00,0xea,0xd1,0x01,0x05,0xc2,0x03]
0x05,0x00,0xea,0xd1,0x01,0x05,0xc2,0x03
-# CHECK: v_mad_f16 v5, -v1, -v2, -v3 ; encoding: [0x05,0x00,0xea,0xd1,0x01,0x05,0x0e,0xe4]
+# VI: v_mad_f16 v5, -v1, -v2, -v3 ; encoding: [0x05,0x00,0xea,0xd1,0x01,0x05,0x0e,0xe4]
0x05,0x00,0xea,0xd1,0x01,0x05,0x0e,0xe4
-# CHECK: v_mad_f16 v5, |v1|, |v2|, |v3| ; encoding: [0x05,0x07,0xea,0xd1,0x01,0x05,0x0e,0x04]
+# VI: v_mad_f16 v5, |v1|, |v2|, |v3| ; encoding: [0x05,0x07,0xea,0xd1,0x01,0x05,0x0e,0x04]
0x05,0x07,0xea,0xd1,0x01,0x05,0x0e,0x04
-# CHECK: v_mad_f16 v5, v1, v2, v3 clamp ; encoding: [0x05,0x80,0xea,0xd1,0x01,0x05,0x0e,0x04]
+# VI: v_mad_f16 v5, v1, v2, v3 clamp ; encoding: [0x05,0x80,0xea,0xd1,0x01,0x05,0x0e,0x04]
0x05,0x80,0xea,0xd1,0x01,0x05,0x0e,0x04
-# CHECK: v_mad_i16 v5, 0.5, v2, v3 ; encoding: [0x05,0x00,0xec,0xd1,0xf0,0x04,0x0e,0x04]
-0x05,0x00,0xec,0xd1,0xf0,0x04,0x0e,0x04
+# VI: v_mad_i16 v5, -1, v2, v3 ; encoding: [0x05,0x00,0xec,0xd1,0xc1,0x04,0x0e,0x04]
+0x05,0x00,0xec,0xd1,0xc1,0x04,0x0e,0x04
-# CHECK: v_mad_i16 v5, v1, 0.5, v3 ; encoding: [0x05,0x00,0xec,0xd1,0x01,0xe1,0x0d,0x04]
-0x05,0x00,0xec,0xd1,0x01,0xe1,0x0d,0x04
+# VI: v_mad_i16 v5, v1, 20, v3 ; encoding: [0x05,0x00,0xec,0xd1,0x01,0x29,0x0d,0x04]
+0x05,0x00,0xec,0xd1,0x01,0x29,0x0d,0x04
-# CHECK: v_mad_i16 v5, v1, v2, 0.5 ; encoding: [0x05,0x00,0xec,0xd1,0x01,0x05,0xc2,0x03]
-0x05,0x00,0xec,0xd1,0x01,0x05,0xc2,0x03
+# VI: v_mad_i16 v5, v1, v2, 63 ; encoding: [0x05,0x00,0xec,0xd1,0x01,0x05,0xfe,0x02]
+0x05,0x00,0xec,0xd1,0x01,0x05,0xfe,0x02
-# CHECK: v_mad_u16 v5, 0, v2, v3 ; encoding: [0x05,0x00,0xeb,0xd1,0x80,0x04,0x0e,0x04]
-0x05,0x00,0xeb,0xd1,0x80,0x04,0x0e,0x04
+# VI: v_mad_u16 v5, -1, v2, v3 ; encoding: [0x05,0x00,0xeb,0xd1,0xc1,0x04,0x0e,0x04]
+0x05,0x00,0xeb,0xd1,0xc1,0x04,0x0e,0x04
-# CHECK: v_mad_u16 v5, v1, -1, v3 ; encoding: [0x05,0x00,0xeb,0xd1,0x01,0x83,0x0d,0x04]
-0x05,0x00,0xeb,0xd1,0x01,0x83,0x0d,0x04
+# VI: v_mad_u16 v5, v1, 20, v3 ; encoding: [0x05,0x00,0xeb,0xd1,0x01,0x29,0x0d,0x04]
+0x05,0x00,0xeb,0xd1,0x01,0x29,0x0d,0x04
-# CHECK: v_mad_u16 v5, v1, v2, -4.0 ; encoding: [0x05,0x00,0xeb,0xd1,0x01,0x05,0xde,0x03]
-0x05,0x00,0xeb,0xd1,0x01,0x05,0xde,0x03
+# VI: v_mad_u16 v5, v1, v2, 63 ; encoding: [0x05,0x00,0xeb,0xd1,0x01,0x05,0xfe,0x02]
+0x05,0x00,0xeb,0xd1,0x01,0x05,0xfe,0x02
# VI: v_interp_mov_f32_e64 v5, p10, attr0.x ; encoding: [0x05,0x00,0x72,0xd2,0x00,0x00,0x00,0x00]
0x05,0x00,0x72,0xd2,0x00,0x00,0x00,0x00
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