[llvm] 548772f - [AArch64] Add additional tests for vector inserts with common element.

[Florian Hahn via llvm-commits]

Author: Florian Hahn
Date: 2020-10-27T14:58:56Z
New Revision: 548772fe69ad518463906300acff5b77a05efe0e

URL: https://github.com/llvm/llvm-project/commit/548772fe69ad518463906300acff5b77a05efe0e
DIFF: https://github.com/llvm/llvm-project/commit/548772fe69ad518463906300acff5b77a05efe0e.diff

LOG: [AArch64] Add additional tests for vector inserts with common element.

Added: 
    

Modified: 
    llvm/test/CodeGen/AArch64/arm64-vector-insertion.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/AArch64/arm64-vector-insertion.ll b/llvm/test/CodeGen/AArch64/arm64-vector-insertion.ll
index 9b0430eff7ab..e5eb1f019b81 100644
--- a/llvm/test/CodeGen/AArch64/arm64-vector-insertion.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-vector-insertion.ll
@@ -31,24 +31,68 @@ entry:
 }
 
 ; TODO: This should jsut be a dup + clearing lane 4.
-define <4 x float> @test2(float %a) {
-; CHECK-LABEL: test2:
+define <4 x float> @test_insert_3_f32_undef_zero_vector(float %a) {
+; CHECK-LABEL: test_insert_3_f32_undef_zero_vector:
+; CHECK:       bb.0:
+; CHECK-NEXT:   movi.2d v1, #0000000000000000
+; CHECK-NEXT:   // kill
+; CHECK-NEXT:   mov.s  v1[0], v0[0]
+; CHECK-NEXT:   mov.s  v1[1], v0[0]
+; CHECK-NEXT:   mov.s  v1[2], v0[0]
+; CHECK-NEXT:   mov.16b v0, v1
+; CHECK-NEXT:   ret
+;
+entry:
+  %0 = insertelement <4 x float> <float undef, float undef, float undef, float 0.000000e+00>, float %a, i32 0
+  %1 = insertelement <4 x float> %0, float %a, i32 1
+  %vecinit3 = insertelement <4 x float> %1, float %a, i32 2
+  ret <4 x float> %vecinit3
+}
+
+define <4 x float> @test_insert_3_f32_undef(float %a) {
+; CHECK-LABEL: test_insert_3_f32_undef:
+; CHECK:       bb.0:
+; CHECK-NEXT:   // kill
+; CHECK-NEXT:   dup.4s  v0, v0[0]
+; CHECK-NEXT:   ret
+;
+entry:
+  %0 = insertelement <4 x float> <float undef, float undef, float undef, float undef>, float %a, i32 0
+  %1 = insertelement <4 x float> %0, float %a, i32 1
+  %vecinit3 = insertelement <4 x float> %1, float %a, i32 2
+  ret <4 x float> %vecinit3
+}
+
+define <4 x float> @test_insert_2_f32_undef_zero(float %a) {
+; CHECK-LABEL: test_insert_2_f32_undef_zero:
 ; CHECK:       bb.0:
 ; CHECK-NEXT:    movi.2d v1, #0000000000000000
 ; CHECK-NEXT:    // kill
 ; CHECK-NEXT:    mov.s  v1[0], v0[0]
-; CHECK-NEXT:    mov.s  v1[1], v0[0]
 ; CHECK-NEXT:    mov.s  v1[2], v0[0]
 ; CHECK-NEXT:    mov.16b v0, v1
 ; CHECK-NEXT:   ret
 ;
 entry:
-  %0 = insertelement <4 x float> <float undef, float undef, float undef, float 0.000000e+00>, float %a, i32 0
-  %1 = insertelement <4 x float> %0, float %a, i32 1
-  %vecinit3 = insertelement <4 x float> %1, float %a, i32 2
+  %0 = insertelement <4 x float> <float undef, float 0.000000e+00, float undef, float 0.000000e+00>, float %a, i32 0
+  %vecinit3 = insertelement <4 x float> %0, float %a, i32 2
   ret <4 x float> %vecinit3
 }
 
+define <4 x float> @test_insert_2_f32_var(float %a, <4 x float> %b) {
+; CHECK-LABEL: test_insert_2_f32_var
+; CHECK:       bb.0:
+; CHECK-NEXT:    // kill
+; CHECK-NEXT:   mov.s  v1[0], v0[0]
+; CHECK-NEXT:   mov.s  v1[2], v0[0]
+; CHECK-NEXT:   mov.16b v0, v1
+; CHECK-NEXT:   ret
+;
+entry:
+  %0 = insertelement <4 x float> %b, float %a, i32 0
+  %vecinit3 = insertelement <4 x float> %0, float %a, i32 2
+  ret <4 x float> %vecinit3
+}
 define <8 x i16> @test_insert_v8i16_i16_zero(<8 x i16> %a) {
 ; CHECK-LABEL: test_insert_v8i16_i16_zero:
 ; CHECK:       bb.0:
@@ -64,9 +108,9 @@ entry:
 define <4 x half> @test_insert_v4f16_f16_zero(<4 x half> %a) {
 ; CHECK-LABEL: test_insert_v4f16_f16_zero:
 ; CHECK:       bb.0:
-; CHECK-NEXT:    adrp    x8, .LCPI4_0
+; CHECK-NEXT:    adrp    x8, .LCPI7_0
 ; CHECK-NEXT:    kill
-; CHECK-NEXT:    add x8, x8, :lo12:.LCPI4_0
+; CHECK-NEXT:    add x8, x8, :lo12:.LCPI7_0
 ; CHECK-NEXT:    ld1.h   { v0 }[0], [x8]
 ; CHECK-NEXT:    kill
 ; CHECK-NEXT:    ret
@@ -79,8 +123,8 @@ entry:
 define <8 x half> @test_insert_v8f16_f16_zero(<8 x half> %a) {
 ; CHECK-LABEL: test_insert_v8f16_f16_zero:
 ; CHECK:       bb.0:
-; CHECK-NEXT:    adrp    x8, .LCPI5_0
-; CHECK-NEXT:    add x8, x8, :lo12:.LCPI5_0
+; CHECK-NEXT:    adrp    x8, .LCPI8_0
+; CHECK-NEXT:    add x8, x8, :lo12:.LCPI8_0
 ; CHECK-NEXT:    ld1.h   { v0 }[6], [x8]
 ; CHECK-NEXT:    ret