[PATCH] D90217: [AMDGPU][GlobalISel] Fold a chain of two shift instructions with constant operands

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


================
Comment at: llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h:57
 
+struct ShiftChain {
+  int64_t Imm;
----------------
Can't this just reuse RegisterImmPair?


================
Comment at: llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-imm-chain.ll:4
+
+define amdgpu_cs i32 @test_shl_1(i32 inreg %arg1) {
+; CHECK-LABEL: test_shl_1:
----------------
These cases are all SGPRs, and don't have any illegal type tests. A few MIR cases wouldn't hurt either


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D90217/new/

https://reviews.llvm.org/D90217