[llvm] bce770f - Revert rG0905bd5c2fa42bd4c "[InstCombine] collectBitParts - add trunc support."

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2020-10-27T13:43:54Z
New Revision: bce770ffa68f11ca67ab8747b1d84567a9934552

URL: https://github.com/llvm/llvm-project/commit/bce770ffa68f11ca67ab8747b1d84567a9934552
DIFF: https://github.com/llvm/llvm-project/commit/bce770ffa68f11ca67ab8747b1d84567a9934552.diff

LOG: Revert rG0905bd5c2fa42bd4c "[InstCombine] collectBitParts - add trunc support."

This reverts commit 0905bd5c2fa42bd4c0e6e0aaa08b966f165b9dfa.

Causing failures in multistage buildbots that I need to investigate

Added: 
    

Modified: 
    llvm/lib/Transforms/Utils/Local.cpp
    llvm/test/Transforms/InstCombine/bswap.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Transforms/Utils/Local.cpp b/llvm/lib/Transforms/Utils/Local.cpp
index d478dfbf8d41..afbba4c83964 100644
--- a/llvm/lib/Transforms/Utils/Local.cpp
+++ b/llvm/lib/Transforms/Utils/Local.cpp
@@ -2931,7 +2931,7 @@ collectBitParts(Value *V, bool MatchBSwaps, bool MatchBitReversals,
       return Result;
     }
 
-    // If this is a zext instruction, zero extend the result.
+    // If this is a zext instruction zero extend the result.
     if (match(V, m_ZExt(m_Value(X)))) {
       const auto &Res =
           collectBitParts(X, MatchBSwaps, MatchBitReversals, BPS, Depth + 1);
@@ -2947,19 +2947,6 @@ collectBitParts(Value *V, bool MatchBSwaps, bool MatchBitReversals,
       return Result;
     }
 
-    // If this is a trunc instruction, take the lower bits.
-    if (match(V, m_Trunc(m_Value(X)))) {
-      const auto &Res =
-          collectBitParts(X, MatchBSwaps, MatchBitReversals, BPS, Depth + 1);
-      if (!Res)
-        return Result;
-
-      Result = BitPart(Res->Provider, BitWidth);
-      for (unsigned BitIdx = 0; BitIdx < BitWidth; ++BitIdx)
-        Result->Provenance[BitIdx] = Res->Provenance[BitIdx];
-      return Result;
-    }
-
     // BITREVERSE - most likely due to us previous matching a partial
     // bitreverse.
     if (match(V, m_BitReverse(m_Value(X)))) {

diff  --git a/llvm/test/Transforms/InstCombine/bswap.ll b/llvm/test/Transforms/InstCombine/bswap.ll
index 8d0adcf15eec..65e2a3607d89 100644
--- a/llvm/test/Transforms/InstCombine/bswap.ll
+++ b/llvm/test/Transforms/InstCombine/bswap.ll
@@ -596,7 +596,19 @@ define i64 @bswap_and_mask_2(i64 %0) {
 
 define i64 @bswap_trunc(i64 %x01234567) {
 ; CHECK-LABEL: @bswap_trunc(
-; CHECK-NEXT:    [[X76543210:%.*]] = call i64 @llvm.bswap.i64(i64 [[X01234567:%.*]])
+; CHECK-NEXT:    [[X7ZZZZZZZ:%.*]] = shl i64 [[X01234567:%.*]], 56
+; CHECK-NEXT:    [[XZ0123456:%.*]] = lshr i64 [[X01234567]], 8
+; CHECK-NEXT:    [[XZZZZZ012:%.*]] = lshr i64 [[X01234567]], 40
+; CHECK-NEXT:    [[X3456:%.*]] = trunc i64 [[XZ0123456]] to i32
+; CHECK-NEXT:    [[XZ012:%.*]] = trunc i64 [[XZZZZZ012]] to i32
+; CHECK-NEXT:    [[X6543:%.*]] = call i32 @llvm.bswap.i32(i32 [[X3456]])
+; CHECK-NEXT:    [[X210Z:%.*]] = call i32 @llvm.bswap.i32(i32 [[XZ012]])
+; CHECK-NEXT:    [[XZ210:%.*]] = lshr exact i32 [[X210Z]], 8
+; CHECK-NEXT:    [[XZZZZ6543:%.*]] = zext i32 [[X6543]] to i64
+; CHECK-NEXT:    [[XZZZZZ210:%.*]] = zext i32 [[XZ210]] to i64
+; CHECK-NEXT:    [[XZ6543ZZZ:%.*]] = shl nuw nsw i64 [[XZZZZ6543]], 24
+; CHECK-NEXT:    [[XZ6543210:%.*]] = or i64 [[XZ6543ZZZ]], [[XZZZZZ210]]
+; CHECK-NEXT:    [[X76543210:%.*]] = or i64 [[XZ6543210]], [[X7ZZZZZZZ]]
 ; CHECK-NEXT:    ret i64 [[X76543210]]
 ;
   %x7zzzzzzz = shl i64 %x01234567, 56