[llvm] 5d03080 - [TargetLowering] Add i1 condition for bit comparison fold

Sven van Haastregt via llvm-commits llvm-commits at lists.llvm.org
Tue Oct 27 05:22:46 PDT 2020


Author: Sven van Haastregt
Date: 2020-10-27T12:22:20Z
New Revision: 5d0308009284a0c8b75fb683eaba89c2e0c677f6

URL: https://github.com/llvm/llvm-project/commit/5d0308009284a0c8b75fb683eaba89c2e0c677f6
DIFF: https://github.com/llvm/llvm-project/commit/5d0308009284a0c8b75fb683eaba89c2e0c677f6.diff

LOG: [TargetLowering] Add i1 condition for bit comparison fold

For i1 types, boolean false is represented identically regardless of
the boolean content, so we can allow optimizations that otherwise
would not be correct for booleans with false represented as a negative
one.

Patch by Erik Hogeman.

Differential Revision: https://reviews.llvm.org/D90145

Added: 
    

Modified: 
    llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    llvm/test/CodeGen/NVPTX/pow2_mask_cmp.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 5a1fc97a9daa..716c571581f4 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -3980,8 +3980,12 @@ SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
     const APInt &C1 = N1C->getAPIntValue();
     EVT ShValTy = N0.getValueType();
 
-    // Fold bit comparisons when we can.
-    if (getBooleanContents(N0.getValueType()) == ZeroOrOneBooleanContent &&
+    // Fold bit comparisons when we can. This will result in an
+    // incorrect value when boolean false is negative one, unless
+    // the bitsize is 1 in which case the false value is the same
+    // in practice regardless of the representation.
+    if ((VT.getSizeInBits() == 1 ||
+         getBooleanContents(N0.getValueType()) == ZeroOrOneBooleanContent) &&
         (Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
         (VT == ShValTy || (isTypeLegal(VT) && VT.bitsLE(ShValTy))) &&
         N0.getOpcode() == ISD::AND) {

diff  --git a/llvm/test/CodeGen/NVPTX/pow2_mask_cmp.ll b/llvm/test/CodeGen/NVPTX/pow2_mask_cmp.ll
index 45701df28a30..824327ebcc74 100644
--- a/llvm/test/CodeGen/NVPTX/pow2_mask_cmp.ll
+++ b/llvm/test/CodeGen/NVPTX/pow2_mask_cmp.ll
@@ -3,14 +3,14 @@
 ; Tests the following pattern:
 ; (X & 8) != 0 --> (X & 8) >> 3
 
-; This produces incorrect code when boolean false is represented
-; as a negative one, and this test checks that the transform is
-; not triggered.
+; This produces incorrect code in general when boolean false is
+; represented as a negative one. There is however a special
+; case when the type has a bitsize of 1, for which the false
+; value will be identical regardless of the boolean representation.
+; Check that the optimization triggers in this case.
 
 ; CHECK-LABEL: @pow2_mask_cmp
-; CHECK: and.b32 [[AND:%r[0-9]+]], %r{{[0-9]+}}, 8
-; CHECK: setp.ne.s32 [[SETP:%p[0-9+]]], [[AND]], 0
-; CHECK: selp.u32 %r{{[0-9]+}}, 1, 0, [[SETP]]
+; CHECK: bfe.u32 {{%r[0-9]+}}, {{%r[0-9]+}}, 3, 1
 define i32 @pow2_mask_cmp(i32 %x) {
   %a = and i32 %x, 8
   %cmp = icmp ne i32 %a, 0


        


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