[llvm] 78a7941 - [TargetRegisterInfo] Fix a couple of typos in the comments

[Quentin Colombet via llvm-commits]

Author: Quentin Colombet
Date: 2020-10-26T15:19:38-07:00
New Revision: 78a7941e5cff263f20f10c51331f575234417f7e

URL: https://github.com/llvm/llvm-project/commit/78a7941e5cff263f20f10c51331f575234417f7e
DIFF: https://github.com/llvm/llvm-project/commit/78a7941e5cff263f20f10c51331f575234417f7e.diff

LOG: [TargetRegisterInfo] Fix a couple of typos in the comments

Spotted by Nicolas Guillemot <nguillemot at apple.com>.

Thanks Nicolas!

NFC

Added: 
    

Modified: 
    llvm/include/llvm/CodeGen/TargetRegisterInfo.h

Removed: 
    


################################################################################
diff  --git a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
index fc3e0ec6faa6..8f60a5fa2ecf 100644
--- a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
@@ -983,7 +983,7 @@ class TargetRegisterInfo : public MCRegisterInfo {
   /// go through this expensive heuristic.
   /// When this target hook is hit, by returning false, there is a high
   /// chance that the register allocation will fail altogether (usually with
-  /// ran out of registers).
+  /// "ran out of registers").
   /// That said, this error usually points to another problem in the
   /// optimization pipeline.
   virtual bool
@@ -992,8 +992,8 @@ class TargetRegisterInfo : public MCRegisterInfo {
     return true;
   }
 
-  /// Deferred spilling delais the spill insertion of a virtual register
-  /// after every other allocations. By deferring the spilling, it is
+  /// Deferred spilling delays the spill insertion of a virtual register
+  /// after every other allocation. By deferring the spilling, it is
   /// sometimes possible to eliminate that spilling altogether because
   /// something else could have been eliminated, thus leaving some space
   /// for the virtual register.