[llvm] ffa6d2a - [DAGCombine] Add test case showing incorrect DAGCombine optimization

[Fraser Cormack via llvm-commits]

Author: Fraser Cormack
Date: 2020-10-26T12:37:31Z
New Revision: ffa6d2afa4a6f35e2e99172a17d489bcec7f0353

URL: https://github.com/llvm/llvm-project/commit/ffa6d2afa4a6f35e2e99172a17d489bcec7f0353
DIFF: https://github.com/llvm/llvm-project/commit/ffa6d2afa4a6f35e2e99172a17d489bcec7f0353.diff

LOG: [DAGCombine] Add test case showing incorrect DAGCombine optimization

This optmization produces incorrect results when the vector element type
is not byte-sized. Related to D78568.

Added: 
    llvm/test/CodeGen/AMDGPU/extract-load-i1.ll

Modified: 
    

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/AMDGPU/extract-load-i1.ll b/llvm/test/CodeGen/AMDGPU/extract-load-i1.ll
new file mode 100644
index 000000000000..14bfe398a12e
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/extract-load-i1.ll
@@ -0,0 +1,18 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=amdgcn-amd-amdhsa < %s | FileCheck %s
+
+; FIXME: Incorrect codegen during an optimization of load + extractelement when
+; the vector element type is not byte-sized: this test loads from %idx-many
+; bytes from address %ptr, instead of that many bits.
+define i1 @extractloadi1(<8 x i1> *%ptr, i32 %idx) {
+; CHECK-LABEL: extractloadi1:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_mad_u64_u32 v[0:1], s[4:5], v2, 1, v[0:1]
+; CHECK-NEXT:    flat_load_ubyte v0, v[0:1]
+; CHECK-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    s_setpc_b64 s[30:31]
+  %val = load <8 x i1>, <8 x i1> *%ptr
+  %ret = extractelement <8 x i1> %val, i32 %idx
+  ret i1 %ret
+}