[llvm] a094b4f - [AMDGPU] Emit new pal metadata by default
Sebastian Neubauer via llvm-commits
llvm-commits at lists.llvm.org
Mon Oct 26 02:16:27 PDT 2020
Author: Sebastian Neubauer
Date: 2020-10-26T10:16:17+01:00
New Revision: a094b4fa4b7f00d3e389a55c401e4078534494b8
URL: https://github.com/llvm/llvm-project/commit/a094b4fa4b7f00d3e389a55c401e4078534494b8
DIFF: https://github.com/llvm/llvm-project/commit/a094b4fa4b7f00d3e389a55c401e4078534494b8.diff
LOG: [AMDGPU] Emit new pal metadata by default
If no pal metadata is given, default to the msgpack format instead of
the legacy metadata. This makes tests better readable.
Differential Revision: https://reviews.llvm.org/D90035
Added:
Modified:
llvm/lib/Target/AMDGPU/Utils/AMDGPUPALMetadata.cpp
llvm/test/CodeGen/AMDGPU/amdpal-cs.ll
llvm/test/CodeGen/AMDGPU/amdpal-es.ll
llvm/test/CodeGen/AMDGPU/amdpal-gs.ll
llvm/test/CodeGen/AMDGPU/amdpal-hs.ll
llvm/test/CodeGen/AMDGPU/amdpal-ls.ll
llvm/test/CodeGen/AMDGPU/amdpal-psenable.ll
llvm/test/CodeGen/AMDGPU/amdpal-vs.ll
llvm/test/CodeGen/AMDGPU/amdpal.ll
llvm/test/CodeGen/AMDGPU/elf-notes.ll
llvm/test/CodeGen/AMDGPU/wave_dispatch_regs.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUPALMetadata.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUPALMetadata.cpp
index ad67d49b100b..12f01faba04b 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUPALMetadata.cpp
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUPALMetadata.cpp
@@ -45,8 +45,11 @@ void AMDGPUPALMetadata::readFromIR(Module &M) {
}
BlobType = ELF::NT_AMD_AMDGPU_PAL_METADATA;
NamedMD = M.getNamedMetadata("amdgpu.pal.metadata");
- if (!NamedMD || !NamedMD->getNumOperands())
+ if (!NamedMD || !NamedMD->getNumOperands()) {
+ // Emit msgpack metadata by default
+ BlobType = ELF::NT_AMDGPU_METADATA;
return;
+ }
// This is the old reg=value pair format for metadata. It is a NamedMD
// containing an MDTuple containing a number of MDNodes each of which is an
// integer value, and each two integer values forms a key=value pair that we
diff --git a/llvm/test/CodeGen/AMDGPU/amdpal-cs.ll b/llvm/test/CodeGen/AMDGPU/amdpal-cs.ll
index 6ffca4c4565e..3a2c5513567a 100644
--- a/llvm/test/CodeGen/AMDGPU/amdpal-cs.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdpal-cs.ll
@@ -2,11 +2,20 @@
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI -enable-var-scope %s
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -enable-var-scope %s
-; amdpal compute shader: check for 0x2e12 (COMPUTE_PGM_RSRC1) in pal metadata
; GCN-LABEL: {{^}}cs_amdpal:
-; GCN: .amd_amdgpu_pal_metadata{{.*}}0x2e12,
+; GCN: .amdgpu_pal_metadata
+; GCN-NEXT: ---
+; GCN-NEXT: amdpal.pipelines:
+; GCN-NEXT: - .hardware_stages:
+; GCN-NEXT: .cs:
+; GCN-NEXT: .entry_point: cs_amdpal
+; GCN-NEXT: .scratch_memory_size: 0
+; GCN: .registers:
+; GCN-NEXT: 0x2e12 (COMPUTE_PGM_RSRC1):
+; GCN-NEXT: 0x2e13 (COMPUTE_PGM_RSRC2):
+; GCN-NEXT: ...
+; GCN-NEXT: .end_amdgpu_pal_metadata
define amdgpu_cs half @cs_amdpal(half %arg0) {
%add = fadd half %arg0, 1.0
ret half %add
}
-
diff --git a/llvm/test/CodeGen/AMDGPU/amdpal-es.ll b/llvm/test/CodeGen/AMDGPU/amdpal-es.ll
index 049e9ae2564e..20354c2e264f 100644
--- a/llvm/test/CodeGen/AMDGPU/amdpal-es.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdpal-es.ll
@@ -1,12 +1,19 @@
; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
-; amdpal evaluation shader: check for 0x2cca (SPI_SHADER_PGM_RSRC1_ES) in pal metadata
; GCN-LABEL: {{^}}es_amdpal:
-; GCN: .amd_amdgpu_pal_metadata{{.*}}0x2cca,
+; GCN: .amdgpu_pal_metadata
+; GCN-NEXT: ---
+; GCN-NEXT: amdpal.pipelines:
+; GCN-NEXT: - .hardware_stages:
+; GCN-NEXT: .es:
+; GCN-NEXT: .entry_point: es_amdpal
+; GCN-NEXT: .scratch_memory_size: 0
+; GCN: .registers:
+; GCN-NEXT: 0x2cca (SPI_SHADER_PGM_RSRC1_ES): 0
+; GCN-NEXT: ...
+; GCN-NEXT: .end_amdgpu_pal_metadata
define amdgpu_es half @es_amdpal(half %arg0) {
%add = fadd half %arg0, 1.0
ret half %add
}
-
-
diff --git a/llvm/test/CodeGen/AMDGPU/amdpal-gs.ll b/llvm/test/CodeGen/AMDGPU/amdpal-gs.ll
index 89e7cf92c1f6..eed38884e7d7 100644
--- a/llvm/test/CodeGen/AMDGPU/amdpal-gs.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdpal-gs.ll
@@ -2,12 +2,19 @@
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -enable-var-scope %s
-; amdpal geometry shader: check for 0x2c8a (SPI_SHADER_PGM_RSRC1_GS) in pal metadata
; GCN-LABEL: {{^}}gs_amdpal:
-; GCN: .amd_amdgpu_pal_metadata{{.*}}0x2c8a,
+; GCN: .amdgpu_pal_metadata
+; GCN-NEXT: ---
+; GCN-NEXT: amdpal.pipelines:
+; GCN-NEXT: - .hardware_stages:
+; GCN-NEXT: .gs:
+; GCN-NEXT: .entry_point: gs_amdpal
+; GCN-NEXT: .scratch_memory_size: 0
+; GCN: .registers:
+; GCN-NEXT: 0x2c8a (SPI_SHADER_PGM_RSRC1_GS): 0
+; GCN-NEXT: ...
+; GCN-NEXT: .end_amdgpu_pal_metadata
define amdgpu_gs half @gs_amdpal(half %arg0) {
%add = fadd half %arg0, 1.0
ret half %add
}
-
-
diff --git a/llvm/test/CodeGen/AMDGPU/amdpal-hs.ll b/llvm/test/CodeGen/AMDGPU/amdpal-hs.ll
index b867717ee237..983c75ffbd59 100644
--- a/llvm/test/CodeGen/AMDGPU/amdpal-hs.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdpal-hs.ll
@@ -2,12 +2,19 @@
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -enable-var-scope %s
-; amdpal hull shader: check for 0x2d0a (SPI_SHADER_PGM_RSRC1_HS) in pal metadata
; GCN-LABEL: {{^}}hs_amdpal:
-; GCN: .amd_amdgpu_pal_metadata{{.*}}0x2d0a,
+; GCN: .amdgpu_pal_metadata
+; GCN-NEXT: ---
+; GCN-NEXT: amdpal.pipelines:
+; GCN-NEXT: - .hardware_stages:
+; GCN-NEXT: .hs:
+; GCN-NEXT: .entry_point: hs_amdpal
+; GCN-NEXT: .scratch_memory_size: 0
+; GCN: .registers:
+; GCN-NEXT: 0x2d0a (SPI_SHADER_PGM_RSRC1_HS): 0
+; GCN-NEXT: ...
+; GCN-NEXT: .end_amdgpu_pal_metadata
define amdgpu_hs half @hs_amdpal(half %arg0) {
%add = fadd half %arg0, 1.0
ret half %add
}
-
-
diff --git a/llvm/test/CodeGen/AMDGPU/amdpal-ls.ll b/llvm/test/CodeGen/AMDGPU/amdpal-ls.ll
index 7168a3c77b87..909a219deb59 100644
--- a/llvm/test/CodeGen/AMDGPU/amdpal-ls.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdpal-ls.ll
@@ -1,12 +1,19 @@
; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
-; amdpal load shader: check for 0x2d4a (SPI_SHADER_PGM_RSRC1_LS) in pal metadata
; GCN-LABEL: {{^}}ls_amdpal:
-; GCN: .amd_amdgpu_pal_metadata{{.*}}0x2d4a,
+; GCN: .amdgpu_pal_metadata
+; GCN-NEXT: ---
+; GCN-NEXT: amdpal.pipelines:
+; GCN-NEXT: - .hardware_stages:
+; GCN-NEXT: .ls:
+; GCN-NEXT: .entry_point: ls_amdpal
+; GCN-NEXT: .scratch_memory_size: 0
+; GCN: .registers:
+; GCN-NEXT: 0x2d4a (SPI_SHADER_PGM_RSRC1_LS): 0
+; GCN-NEXT: ...
+; GCN-NEXT: .end_amdgpu_pal_metadata
define amdgpu_ls half @ls_amdpal(half %arg0) {
%add = fadd half %arg0, 1.0
ret half %add
}
-
-
diff --git a/llvm/test/CodeGen/AMDGPU/amdpal-psenable.ll b/llvm/test/CodeGen/AMDGPU/amdpal-psenable.ll
index c1494d0d4c43..5deb0661f4e3 100644
--- a/llvm/test/CodeGen/AMDGPU/amdpal-psenable.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdpal-psenable.ll
@@ -6,7 +6,20 @@
; end up with an interpolation mode set in PSAddr but not PSEnable. This test tests
; the workaround that ensures that an interpolation mode is also set in PSEnable.
; GCN-LABEL: {{^}}amdpal_psenable:
-; GCN: .amd_amdgpu_pal_metadata{{.*}}0xa1b3,0x2,0xa1b4,0x2,
+; GCN: .amdgpu_pal_metadata
+; GCN-NEXT: ---
+; GCN-NEXT: amdpal.pipelines:
+; GCN-NEXT: - .hardware_stages:
+; GCN-NEXT: .ps:
+; GCN-NEXT: .entry_point: amdpal_psenable
+; GCN-NEXT: .scratch_memory_size: 0
+; GCN: .registers:
+; GCN-NEXT: 0x2c0a (SPI_SHADER_PGM_RSRC1_PS):
+; GCN-NEXT: 0x2c0b (SPI_SHADER_PGM_RSRC2_PS):
+; GCN-NEXT: 0xa1b3 (SPI_PS_INPUT_ENA): 0x2
+; GCN-NEXT: 0xa1b4 (SPI_PS_INPUT_ADDR): 0x2
+; GCN-NEXT: ...
+; GCN-NEXT: .end_amdgpu_pal_metadata
define amdgpu_ps void @amdpal_psenable(i32 inreg, i32 inreg, i32 inreg, i32 inreg %m0, <2 x float> %pos) #6 {
%inst23 = extractelement <2 x float> %pos, i32 0
%inst24 = extractelement <2 x float> %pos, i32 1
diff --git a/llvm/test/CodeGen/AMDGPU/amdpal-vs.ll b/llvm/test/CodeGen/AMDGPU/amdpal-vs.ll
index a13205dabd04..9bcd36384756 100644
--- a/llvm/test/CodeGen/AMDGPU/amdpal-vs.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdpal-vs.ll
@@ -2,12 +2,19 @@
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -enable-var-scope %s
-; amdpal vertex shader: check for 45352 (SPI_SHADER_PGM_RSRC1_VS) in pal metadata
; GCN-LABEL: {{^}}vs_amdpal:
-; GCN: .amd_amdgpu_pal_metadata{{.*}}0x2c4a,
+; GCN: .amdgpu_pal_metadata
+; GCN-NEXT: ---
+; GCN-NEXT: amdpal.pipelines:
+; GCN-NEXT: - .hardware_stages:
+; GCN-NEXT: .vs:
+; GCN-NEXT: .entry_point: vs_amdpal
+; GCN-NEXT: .scratch_memory_size: 0
+; GCN: .registers:
+; GCN-NEXT: 0x2c4a (SPI_SHADER_PGM_RSRC1_VS): 0
+; GCN-NEXT: ...
+; GCN-NEXT: .end_amdgpu_pal_metadata
define amdgpu_vs half @vs_amdpal(half %arg0) {
%add = fadd half %arg0, 1.0
ret half %add
}
-
-
diff --git a/llvm/test/CodeGen/AMDGPU/amdpal.ll b/llvm/test/CodeGen/AMDGPU/amdpal.ll
index 7d6f010f0b4d..b6c7fcec9f94 100644
--- a/llvm/test/CodeGen/AMDGPU/amdpal.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdpal.ll
@@ -86,5 +86,12 @@ attributes #0 = { nounwind "amdgpu-git-ptr-high"="0x1234" }
declare void @llvm.amdgcn.raw.buffer.store.f32(float, <4 x i32>, i32, i32, i32 immarg)
-; Check we have CS_NUM_USED_VGPRS in PAL metadata.
-; PAL: .amd_amdgpu_pal_metadata {{.*}},0x10000027,
+; PAL: .amdgpu_pal_metadata
+; PAL-NEXT: ---
+; PAL-NEXT: amdpal.pipelines:
+; PAL-NEXT: - .hardware_stages:
+; PAL-NEXT: .cs:
+; PAL-NEXT: .entry_point: scratch2_cs
+; PAL-NEXT: .scratch_memory_size: 0x10
+; PAL-NEXT: .sgpr_count: 0x
+; PAL-NEXT: .vgpr_count: 0x
diff --git a/llvm/test/CodeGen/AMDGPU/elf-notes.ll b/llvm/test/CodeGen/AMDGPU/elf-notes.ll
index b49fd010bb5e..fa262752fbc7 100644
--- a/llvm/test/CodeGen/AMDGPU/elf-notes.ll
+++ b/llvm/test/CodeGen/AMDGPU/elf-notes.ll
@@ -57,18 +57,34 @@
; OSABI-PAL: .hsa_code_object_isa
; OSABI-PAL: .amd_amdgpu_isa "amdgcn-amd-amdpal--gfx802"
; OSABI-PAL-NOT: .amd_amdgpu_hsa_metadata
-; OSABI-PAL: .amd_amdgpu_pal_metadata
; OSABI-PAL-ELF: Unknown note type: (0x00000003)
; OSABI-PAL-ELF: NT_AMD_AMDGPU_ISA (ISA Version)
; OSABI-PAL-ELF: ISA Version:
; OSABI-PAL-ELF: amdgcn-amd-amdpal--gfx802
; OSABI-PAL-ELF-NOT: NT_AMD_AMDGPU_HSA_METADATA (HSA Metadata)
-; OSABI-PAL-ELF: NT_AMD_AMDGPU_PAL_METADATA (PAL Metadata)
-; TODO: readobj can no longer dump PAL metadata pending resolution of D52821
-; OSABI-PAL-ELF-XXX: PAL Metadata:
-; TODO: Following check line fails on mips:
-; OSABI-PAL-ELF-XXX: 0x2e12,0xac02c0,0x2e13,0x80,0x1000001b,0x1,0x10000022,0x60,0x1000003e,0x0
+; OSABI-PAL-ELF: NT_AMDGPU_METADATA (AMDGPU Metadata)
+; OSABI-PAL-ELF: AMDGPU Metadata:
+; OSABI-PAL-ELF: amdpal.pipelines:
+; OSABI-PAL-ELF: - .hardware_stages:
+; OSABI-PAL-ELF: .cs:
+; OSABI-PAL-ELF: .entry_point: elf_notes
+; OSABI-PAL-ELF: .scratch_memory_size: 0
+; OSABI-PAL-ELF: .sgpr_count: 96
+; OSABI-PAL-ELF: .vgpr_count: 1
+; OSABI-PAL-ELF: .registers:
+; OSABI-PAL-ELF: 11794: 11469504
+; OSABI-PAL-ELF: 11795: 128
+; OSABI-PAL: amdpal.pipelines:
+; OSABI-PAL: - .hardware_stages:
+; OSABI-PAL: .cs:
+; OSABI-PAL: .entry_point: elf_notes
+; OSABI-PAL: .scratch_memory_size: 0
+; OSABI-PAL: .sgpr_count: 0x60
+; OSABI-PAL: .vgpr_count: 0x1
+; OSABI-PAL: .registers:
+; OSABI-PAL: 0x2e12 (COMPUTE_PGM_RSRC1): 0xaf02c0
+; OSABI-PAL: 0x2e13 (COMPUTE_PGM_RSRC2): 0x80
; R600-NOT: .hsa_code_object_version
; R600-NOT: .hsa_code_object_isa
diff --git a/llvm/test/CodeGen/AMDGPU/wave_dispatch_regs.ll b/llvm/test/CodeGen/AMDGPU/wave_dispatch_regs.ll
index 06174f8b8583..e73235857728 100644
--- a/llvm/test/CodeGen/AMDGPU/wave_dispatch_regs.ll
+++ b/llvm/test/CodeGen/AMDGPU/wave_dispatch_regs.ll
@@ -7,12 +7,28 @@
; are set to reflect that, even though the registers are not used in the shader.
; GCN-LABEL: {{^}}_amdgpu_cs_main:
-; SI: .amd_amdgpu_pal_metadata{{.*}}0x2e12,0x{{[0-9a-f]*}}81,
-; VI: .amd_amdgpu_pal_metadata{{.*}}0x2e12,0x{{[0-9a-f]*}}c1,
-; GFX9: .amd_amdgpu_pal_metadata{{.*}}0x2e12,0x{{[0-9a-f]*}}81,
+; GCN: .amdgpu_pal_metadata
+; GCN-NEXT: ---
+; GCN-NEXT: amdpal.pipelines:
+; GCN-NEXT: - .hardware_stages:
+; GCN-NEXT: .cs:
+; GCN-NEXT: .entry_point: _amdgpu_cs_main
+; GCN-NEXT: .scratch_memory_size: 0
+; SI-NEXT: .sgpr_count: 0x11
+; VI-NEXT: .sgpr_count: 0x60
+; GFX9-NEXT: .sgpr_count: 0x11
+; SI-NEXT: .vgpr_count: 0x5
+; VI-NEXT: .vgpr_count: 0x5
+; GFX9-NEXT: .vgpr_count: 0x5
+; GCN-NEXT: .registers:
+; SI-NEXT: 0x2e12 (COMPUTE_PGM_RSRC1): 0x{{[0-9a-f]*}}81
+; VI-NEXT: 0x2e12 (COMPUTE_PGM_RSRC1): 0x{{[0-9a-f]*}}c1
+; GFX9-NEXT: 0x2e12 (COMPUTE_PGM_RSRC1): 0x{{[0-9a-f]*}}81
+; GCN-NEXT: 0x2e13 (COMPUTE_PGM_RSRC2): 0
+; GCN-NEXT: ...
+; GCN-NEXT: .end_amdgpu_pal_metadata
define dllexport amdgpu_cs void @_amdgpu_cs_main(i32 inreg, i32 inreg, <2 x i32> inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, <3 x i32> inreg, i32 inreg, <5 x i32>) {
.entry:
ret void
}
-
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