[PATCH] D89084: [PowerPC] Combine select_cc (x, 0, t, f, lt) to avoid generating `isel`

[ChenZheng via Phabricator via llvm-commits]

shchenz added a comment.

I guess this opt should also be profitable for opcode `SELECT`, is there any reason we don't do this?



================
Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:13599
+  // where (z - y) is power of 2.
+  if (VT.isInteger() && TrueC && FalseC && isTypeLegal(VT) &&
+      (isNullConstant(RHS) && CC == ISD::SETLT)) {
----------------
is it possible to put some conditions in early returns and put some comments there?


================
Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:13608
+    APInt AbsDiff = Diff.abs();
+    if (!OV && AbsDiff.isPowerOf2() && CompVT.isInteger() &&
+        isTypeLegal(CompVT)) {
----------------
same as above, put some contidions in early returns and put some comments there?


================
Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:13614
+                      DAG.getConstant(SignBitShiftAmount, DL, CompVT));
+      if (CompVT.getSizeInBits() < VT.getSizeInBits())
+        SignBit = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, SignBit);
----------------
can `getZExtOrTrunc` be used here?


Repository:
  rG LLVM Github Monorepo

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https://reviews.llvm.org/D89084