[llvm] 5e9f172 - [InstCombine] Add test for or(fshl(), fshl()) bswap pattern.

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2020-10-25T10:07:19Z
New Revision: 5e9f172295d011cc0a186a3e133b3b628556287f

URL: https://github.com/llvm/llvm-project/commit/5e9f172295d011cc0a186a3e133b3b628556287f
DIFF: https://github.com/llvm/llvm-project/commit/5e9f172295d011cc0a186a3e133b3b628556287f.diff

LOG: [InstCombine] Add test for or(fshl(),fshl()) bswap pattern.

Currently InstCombinerImpl::matchBSwapOrBitReverse won't match starting from funnel shifts.

Added: 
    

Modified: 
    llvm/test/Transforms/InstCombine/bswap.ll

Removed: 
    


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diff  --git a/llvm/test/Transforms/InstCombine/bswap.ll b/llvm/test/Transforms/InstCombine/bswap.ll
index effbc66499c0..f0a322d58913 100644
--- a/llvm/test/Transforms/InstCombine/bswap.ll
+++ b/llvm/test/Transforms/InstCombine/bswap.ll
@@ -685,6 +685,23 @@ define i32 @funnel_binary(i32 %abcd) {
   ret i32 %dcba
 }
 
+define i32 @funnel_and(i32 %abcd) {
+; CHECK-LABEL: @funnel_and(
+; CHECK-NEXT:    [[ZZCZ:%.*]] = and i32 [[ABCD:%.*]], 65280
+; CHECK-NEXT:    [[ZCZA:%.*]] = call i32 @llvm.fshl.i32(i32 [[ZZCZ]], i32 [[ABCD]], i32 8)
+; CHECK-NEXT:    [[ZBZZ:%.*]] = and i32 [[ABCD]], 16711680
+; CHECK-NEXT:    [[DZBZ:%.*]] = call i32 @llvm.fshl.i32(i32 [[ABCD]], i32 [[ZBZZ]], i32 24)
+; CHECK-NEXT:    [[DCBA:%.*]] = or i32 [[ZCZA]], [[DZBZ]]
+; CHECK-NEXT:    ret i32 [[DCBA]]
+;
+  %zzcz = and i32 %abcd, 65280
+  %zcza = call i32 @llvm.fshl.i32(i32 %zzcz, i32 %abcd, i32 8)
+  %zbzz = and i32 %abcd, 16711680
+  %dzbz = call i32 @llvm.fshl.i32(i32 %abcd, i32 %zbzz, i32 24)
+  %dcba = or i32 %zcza, %dzbz
+  ret i32 %dcba
+}
+
 ; PR47191 - deep IR trees prevent ADD/XOR instructions being simplified to OR.
 
 define i64 @PR47191_problem1(i64 %0) {