[PATCH] D90092: [AVR] Optimize 16-bit int shift

[Ben Shi via Phabricator via llvm-commits]

benshi001 created this revision.
benshi001 added reviewers: dylanmckay, aykevl.
Herald added subscribers: llvm-commits, Jim, hiraditya.
Herald added a project: LLVM.
benshi001 requested review of this revision.

Optimize "Rd+1:Rd << 8" to

  mov Rd+1, Rd
  clr Rd

Optimize (logic) "Rd+1:Rd >> 8" to

  mov Rd, Rd+1
  clr Rd+1

Optimize (arithmetic) "Rd+1:Rd >> 8" to

  mov Rd, Rd+1
  lsl Rd+1
  sbc Rd+1, Rd+1


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D90092

Files:
  llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp
  llvm/lib/Target/AVR/AVRISelLowering.cpp
  llvm/lib/Target/AVR/AVRISelLowering.h
  llvm/lib/Target/AVR/AVRInstrInfo.td
  llvm/test/CodeGen/AVR/shift.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D90092.300469.patch
Type: text/x-patch
Size: 9450 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20201024/435ad40c/attachment.bin>