[PATCH] D90024: [ARM][SchedModels] Get rid of IsLdrAm2ScaledPred

[Eugene Leviant via Phabricator via llvm-commits]

evgeny777 added a comment.

> (paranoia level).
> Are we sure that the lowering of MachineInstr to MCInst is preserving the operand sequence? Can it be that the immediate is at position 4 for the MCInst only?
> I have no idea how an ldrbt looks like as a MachineInstr. The original check should have triggered an assertion too for MachineInstr then...

@andreadb Well, it's interesting thought and I, honestly, do not know. However with LDRBT it doesn't seem to be the case. Here is handwritten MIR:

  name:            test_ldrbt
  tracksRegLiveness: true
  body: |
    bb.0:
      liveins: $r1, $r3, $r4
      %1:gprnopc = COPY $r1
      %3:gprnopc = COPY $r3
      %4:gprnopc = COPY $r4
      %3:gprnopc, %4:gprnopc = LDRBT_POST_REG %4:gprnopc, %1:gprnopc, 20492, 0, $noreg
  
      $r0 = COPY %3:gprnopc
      BX_RET 14, $noreg, implicit $r0

If you're interested you can try transforming it to asm with `llc -start-before=greedy -filetype=asm ...` and check operand sequence in assembly with `llvm-mc --debug`


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  https://reviews.llvm.org/D90024/new/

https://reviews.llvm.org/D90024