[PATCH] D90024: [ARM][SchedModels] Get rid of IsLdrAm2ScaledPred

Eugene Leviant via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Fri Oct 23 08:48:40 PDT 2020

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evgeny777 added a comment.

> Should it always have been checking operand 4 then? I think that makes sense

IMO, it was incorrectly checking for operand 3. I've got an assertion when switched to MC pred


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  https://reviews.llvm.org/D90024/new/

https://reviews.llvm.org/D90024

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