[PATCH] D89162: [SVE] Lower fixed length VECREDUCE_SEQ_FADD operation

[Nikita Popov via Phabricator via llvm-commits]

nikic requested changes to this revision.
nikic added a comment.
This revision now requires changes to proceed.

This should be split into two parts:

1. A patch that implements **all** the necessary legalizations for VECREDUCE_SEQ_* and enables use of SDAG legalization on AArch64 (and possibly ARM) unconditionally. This may need some additional test coverage to trigger all possible legalizations. Necessary legalizations also include float legalization, not just vector legalization.
2. A patch that adds improved lowerings using SVE instructions based on that.


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  https://reviews.llvm.org/D89162/new/

https://reviews.llvm.org/D89162