[PATCH] D90045: [ARM][SchedModels] Convert IsLdrAm3NegRegOffPred to MCSchedPredicate

[Andrea Di Biagio via Phabricator via llvm-commits]

andreadb added inline comments.


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Comment at: llvm/lib/Target/ARM/ARMScheduleA57.td:37
+def IsLdrAm3NegRegOffPred : MCSchedPredicate<CheckAll<[
+                              CheckIsRegOperand<2>,
+                              CheckAM3OpSub<3>]>>;
----------------
You also need to check that the operand is not the invalid register.
So, something like: CheckNot<CheckInvalidRegOperand<2>>.

As a side note: it might be worthy to add a helper MCSchedPredicate named `CheckIsValidRegOperand` which is basically a shorthand for 
`CheckNot<CheckInvalidRegOperand<n>>`.


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Comment at: llvm/lib/Target/ARM/ARMScheduleA57.td:40
+def IsLdrAm3NegRegOffPredX2 : MCSchedPredicate<CheckAll<[
+                                CheckIsRegOperand<3>,
+                                CheckAM3OpSub<4>]>>;
----------------
Same.


================
Comment at: llvm/lib/Target/ARM/ARMScheduleA57.td:42-44
+def IsLdrAm3NegRegOffPredX3 : MCSchedPredicate<CheckAll<[
+                                CheckIsRegOperand<4>,
+                                CheckAM3OpSub<5>]>>;
----------------
Same.

By the way: the  `CheckAll <CheckIsRegOperand, CheckAM3OpSub>` sequence is a repeated three times (one per each definition).
You could add a template class which expands to that predicate sequence? Just an idea.


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  https://reviews.llvm.org/D90045/new/

https://reviews.llvm.org/D90045