[PATCH] D89449: [RISCV] Initial infrastructure for code generation of the RISC-V V-extension

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.td:255
+// this approach assumes that VLEN>=64.
+// Additionally, the only supported ELEN values are 32 and 64,
+// thus `vscale` can be defined as VLEN/64,
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Perhaps it would be good to explain in the code if/how an implementation with `ELEN<32` or `ELEN>64` could/would be supported, as there's bound to be one some day. For example, is it impossible, is it incompatible, is it awkward, or are there just performance implications? Basically, what are the tradeoffs to the imposed constraints? The RFC goes a little bit into that regarding `i128` but that might get lost in time.


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  rL LLVM

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  https://reviews.llvm.org/D89449/new/

https://reviews.llvm.org/D89449