[llvm] cb86522 - [ARM][SchedModels] Convert IsR1P0AndLaterPred to MCSchedPredicate. NFC

[Evgeny Leviant via llvm-commits]

Author: Evgeny Leviant
Date: 2020-10-23T14:27:49+03:00
New Revision: cb86522c9450d909863d36cd73dae2586f82fcdb

URL: https://github.com/llvm/llvm-project/commit/cb86522c9450d909863d36cd73dae2586f82fcdb
DIFF: https://github.com/llvm/llvm-project/commit/cb86522c9450d909863d36cd73dae2586f82fcdb.diff

LOG: [ARM][SchedModels] Convert IsR1P0AndLaterPred to MCSchedPredicate. NFC

Differential revision: https://reviews.llvm.org/D90017

Added: 
    

Modified: 
    llvm/lib/Target/ARM/ARMScheduleA57.td

Removed: 
    


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diff  --git a/llvm/lib/Target/ARM/ARMScheduleA57.td b/llvm/lib/Target/ARM/ARMScheduleA57.td
index 2357383942fe..bca992fbbfcc 100644
--- a/llvm/lib/Target/ARM/ARMScheduleA57.td
+++ b/llvm/lib/Target/ARM/ARMScheduleA57.td
@@ -26,7 +26,7 @@ def IsCPSRDefinedAndPredicatedPred :
     MCSchedPredicate<IsCPSRDefinedAndPredicated>;
 
 // Cortex A57 rev. r1p0 or later (false = r0px)
-def IsR1P0AndLaterPred : SchedPredicate<[{false}]>;
+def IsR1P0AndLaterPred : MCSchedPredicate<FalsePred>;
 
 def IsLdrAm3RegOffPred : MCSchedPredicate<CheckInvalidRegOperand<2>>;
 def IsLdrAm3RegOffPredX2 : MCSchedPredicate<CheckInvalidRegOperand<3>>;