[PATCH] D90009: [X86] VEX/EVEX prefix doesn't work for inline assembly.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp:3896
+    // encoder.
     Prefixes |= X86::IP_USE_VEX3;
+    Prefixes |= X86::Force_VEX3Encoding;
----------------
LiuChen3 wrote:
> craig.topper wrote:
> > Why do we need Force_VEX3Encoding and IP_USE_VEX3?
> I think this will make all of IP_USE_VEX3 the 3-byte vex prefix instruction output with {vex3}. The IP_USE_VEX3 is for encoder.
Isn't this the only place we set IP_USE_VEX3?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D90009/new/

https://reviews.llvm.org/D90009