[PATCH] D90009: [X86] VEX/EVEX prefix doesn't work for inline assembly.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp:3896
+    // encoder.
     Prefixes |= X86::IP_USE_VEX3;
+    Prefixes |= X86::Force_VEX3Encoding;
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Why do we need Force_VEX3Encoding and IP_USE_VEX3?


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Comment at: llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h:67
+    IP_USE_DISP32 = 1U << 8,
+    Force_VEXEncoding = 1U << 9,
+    Force_VEX2Encoding = 1U << 10,
----------------
Why don't these start with IP_?


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Comment at: llvm/lib/Target/X86/MCTargetDesc/X86InstPrinterCommon.cpp:354
+  else if (Flags & X86::Force_VEX2Encoding)
+    O << "\t{vex2}";
+  else if (Flags & X86::Force_VEX3Encoding)
----------------
Is it important that we use {vex2} instead of just treating it as {vex}?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D90009/new/

https://reviews.llvm.org/D90009