[llvm] 3fbf9d1 - [gn build] (semi-manually) port 147b9497e79

[Nico Weber via llvm-commits]

Author: Nico Weber
Date: 2020-10-22T18:19:59-04:00
New Revision: 3fbf9d10fdf21abedfd68bf53ad7098c00c6850c

URL: https://github.com/llvm/llvm-project/commit/3fbf9d10fdf21abedfd68bf53ad7098c00c6850c
DIFF: https://github.com/llvm/llvm-project/commit/3fbf9d10fdf21abedfd68bf53ad7098c00c6850c.diff

LOG: [gn build] (semi-manually) port 147b9497e79

Added: 
    

Modified: 
    llvm/utils/gn/secondary/llvm/lib/Target/AArch64/BUILD.gn

Removed: 
    


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diff  --git a/llvm/utils/gn/secondary/llvm/lib/Target/AArch64/BUILD.gn b/llvm/utils/gn/secondary/llvm/lib/Target/AArch64/BUILD.gn
index 78d75d540fc4..919a16829414 100644
--- a/llvm/utils/gn/secondary/llvm/lib/Target/AArch64/BUILD.gn
+++ b/llvm/utils/gn/secondary/llvm/lib/Target/AArch64/BUILD.gn
@@ -48,6 +48,15 @@ tablegen("AArch64GenPreLegalizeGICombiner") {
   td_file = "AArch64.td"
 }
 
+tablegen("AArch64GenPostLegalizeGILowering") {
+  visibility = [ ":LLVMAArch64CodeGen" ]
+  args = [
+    "-gen-global-isel-combiner",
+    "-combiners=AArch64PostLegalizerLoweringHelper",
+  ]
+  td_file = "AArch64.td"
+}
+
 tablegen("AArch64GenRegisterBank") {
   visibility = [ ":LLVMAArch64CodeGen" ]
   args = [ "-gen-register-bank" ]
@@ -63,6 +72,7 @@ static_library("LLVMAArch64CodeGen") {
     ":AArch64GenMCPseudoLowering",
     ":AArch64GenPostLegalizeGICombiner",
     ":AArch64GenPreLegalizeGICombiner",
+    ":AArch64GenPostLegalizeGILowering",
     ":AArch64GenRegisterBank",
 
     # See https://reviews.llvm.org/D69130
@@ -129,6 +139,7 @@ static_library("LLVMAArch64CodeGen") {
     "GISel/AArch64InstructionSelector.cpp",
     "GISel/AArch64LegalizerInfo.cpp",
     "GISel/AArch64PostLegalizerCombiner.cpp",
+    "GISel/AArch64PostLegalizerLowering.cpp",
     "GISel/AArch64PreLegalizerCombiner.cpp",
     "GISel/AArch64RegisterBankInfo.cpp",
     "SVEIntrinsicOpts.cpp",