[PATCH] D89957: [ARM][SchedModels] Let ldm* instruction scheduling use MCSchedPredicate

[Eugene Leviant via Phabricator via llvm-commits]

evgeny777 added inline comments.


================
Comment at: llvm/lib/Target/ARM/ARMScheduleA57.td:515
+  def A57LMAddrPred#NumAddr : MCSchedPredicate<CheckAny<[
+                                CheckNumOperands<!add(!shl(NumAddr, 1), 2)>,
+                                CheckNumOperands<!add(!shl(NumAddr, 1), 3)>]>>;
----------------
dmgreen wrote:
> Can you explain the operands this uses? Two from the predicate, And then N*2 for the variable number of regs split into groups of 2?
> 
> I think the _UPD forms will have an extra operand, and LDMIA looks like it has 3 + 2*N.
>   t2LDMIA killed $lr, 14 /* CC::al */, $noreg, def $r2, def $r3
> vs
>   $sp = t2LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r7, def $lr
> Can you explain the operands this uses? Two from the predicate, And then N*2 for the variable number of regs split into groups of 2?

Normal (no update) forms of LDM have N + 3 operands, where N is number of memory accesses. Cortex-a57 model defines same write lists for N and N+1 memory accesses, where N is odd. So `A57LMAddrPred1` will trigger for N = 1 and N = 2 (with total number of operands being 4 and 5 respectively), `A57LMAddrPred2` for N = 3 and N = 4 and so on

> I think the _UPD forms will have an extra operand, and LDMIA looks like it has 3 + 2*N

Right, that's a bug. I'll update the diff.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D89957/new/

https://reviews.llvm.org/D89957