[llvm] ed6a91f - [ARM][SchedModels] Convert IsLdstsoScaledPred to MCSchedPredicate
Evgeny Leviant via llvm-commits
llvm-commits at lists.llvm.org
Thu Oct 22 08:03:22 PDT 2020
Author: Evgeny Leviant
Date: 2020-10-22T18:03:01+03:00
New Revision: ed6a91f4567ead72ffb34975863575348ecf0674
URL: https://github.com/llvm/llvm-project/commit/ed6a91f4567ead72ffb34975863575348ecf0674
DIFF: https://github.com/llvm/llvm-project/commit/ed6a91f4567ead72ffb34975863575348ecf0674.diff
LOG: [ARM][SchedModels] Convert IsLdstsoScaledPred to MCSchedPredicate
Differential revision: https://reviews.llvm.org/D89939
Added:
Modified:
llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
llvm/lib/Target/ARM/ARMBaseInstrInfo.h
llvm/lib/Target/ARM/ARMSchedule.td
llvm/lib/Target/ARM/ARMScheduleA57.td
llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
llvm/test/tools/llvm-mca/ARM/cortex-a57-memory-instructions.s
Removed:
################################################################################
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
index 0632e1be2fc9..817bc3363a11 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -626,13 +626,6 @@ bool ARMBaseInstrInfo::isAddrMode3OpMinusReg(const MachineInstr &MI,
return (isSub && Offset.getReg() != 0);
}
-bool ARMBaseInstrInfo::isLdstScaledReg(const MachineInstr &MI,
- unsigned Op) const {
- const MachineOperand &Opc = MI.getOperand(Op + 2);
- unsigned OffImm = Opc.getImm();
- return ARM_AM::getAM2ShiftOpc(OffImm) != ARM_AM::no_shift;
-}
-
// Load, scaled register offset, not plus LSL2
bool ARMBaseInstrInfo::isLdstScaledRegNotPlusLsl2(const MachineInstr &MI,
unsigned Op) const {
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
index f894a85c914f..a03d57c97d5e 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
@@ -180,8 +180,6 @@ class ARMBaseInstrInfo : public ARMGenInstrInfo {
static bool isCPSRDefined(const MachineInstr &MI);
bool isAddrMode3OpMinusReg(const MachineInstr &MI, unsigned Op) const;
- // Load, scaled register offset
- bool isLdstScaledReg(const MachineInstr &MI, unsigned Op) const;
// Load, scaled register offset, not plus LSL2
bool isLdstScaledRegNotPlusLsl2(const MachineInstr &MI, unsigned Op) const;
// Minus reg for ldstso addr mode
diff --git a/llvm/lib/Target/ARM/ARMSchedule.td b/llvm/lib/Target/ARM/ARMSchedule.td
index 8cdf12a625ce..23cbf6b6c0be 100644
--- a/llvm/lib/Target/ARM/ARMSchedule.td
+++ b/llvm/lib/Target/ARM/ARMSchedule.td
@@ -164,6 +164,10 @@ def IsCPSRDefined : CheckFunctionPredicateWithTII<
def IsCPSRDefinedPred : MCSchedPredicate<IsCPSRDefined>;
+let FunctionMapper = "ARM_AM::getAM2ShiftOpc" in {
+ def CheckExtNoShift : CheckImmOperand_s<4, "ARM_AM::no_shift">;
+}
+
//===----------------------------------------------------------------------===//
// Instruction Itinerary classes used for ARM
//
diff --git a/llvm/lib/Target/ARM/ARMScheduleA57.td b/llvm/lib/Target/ARM/ARMScheduleA57.td
index 1a9de1d9fb78..99a31055645a 100644
--- a/llvm/lib/Target/ARM/ARMScheduleA57.td
+++ b/llvm/lib/Target/ARM/ARMScheduleA57.td
@@ -49,11 +49,7 @@ def IsLdstsoScaledNotOptimalPred :
def IsLdstsoScaledNotOptimalPredX2 :
SchedPredicate<[{TII->isLdstScaledRegNotPlusLsl2(*MI, 2)}]>;
-// Load, scaled register offset
-def IsLdstsoScaledPred :
- SchedPredicate<[{TII->isLdstScaledReg(*MI, 1)}]>;
-def IsLdstsoScaledPredX2 :
- SchedPredicate<[{TII->isLdstScaledReg(*MI, 2)}]>;
+def IsLdstsoScaledPredX2 : MCSchedPredicate<CheckNot<CheckExtNoShift>>;
def IsLdstsoMinusRegPredX0 :
SchedPredicate<[{TII->isLdstSoMinusReg(*MI, 0)}]>;
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
index 293c2d639f88..774f2507b8d2 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
@@ -11,6 +11,7 @@
//===----------------------------------------------------------------------===//
#include "ARMMCTargetDesc.h"
+#include "ARMAddressingModes.h"
#include "ARMBaseInfo.h"
#include "ARMInstPrinter.h"
#include "ARMMCAsmInfo.h"
diff --git a/llvm/test/tools/llvm-mca/ARM/cortex-a57-memory-instructions.s b/llvm/test/tools/llvm-mca/ARM/cortex-a57-memory-instructions.s
index 1def95ee1120..d1e0880506d7 100644
--- a/llvm/test/tools/llvm-mca/ARM/cortex-a57-memory-instructions.s
+++ b/llvm/test/tools/llvm-mca/ARM/cortex-a57-memory-instructions.s
@@ -261,7 +261,7 @@
# CHECK-NEXT: 1 1 1.00 * str r9, [r6, r3]
# CHECK-NEXT: 1 1 1.00 * str r8, [r0, -r2]
# CHECK-NEXT: 2 1 1.00 * str r7, [r1, r6]!
-# CHECK-NEXT: 2 1 1.00 * str r7, [r1, r6, lsl #2]!
+# CHECK-NEXT: 2 2 1.00 * str r7, [r1, r6, lsl #2]!
# CHECK-NEXT: 2 1 1.00 * str r6, [sp, -r1]!
# CHECK-NEXT: 2 2 1.00 * str r5, [r3], r9
# CHECK-NEXT: 2 2 1.00 * str r4, [r2], -r5
@@ -321,7 +321,7 @@
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1.0] [1.1] [2] [3] [4] [5] [6]
-# CHECK-NEXT: - 44.50 44.50 284.00 8.00 55.00 - -
+# CHECK-NEXT: - 44.00 44.00 284.00 9.00 55.00 - -
# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1.0] [1.1] [2] [3] [4] [5] [6] Instructions:
@@ -426,7 +426,7 @@
# CHECK-NEXT: - - - - - 1.00 - - str r9, [r6, r3]
# CHECK-NEXT: - - - - - 1.00 - - str r8, [r0, -r2]
# CHECK-NEXT: - 0.50 0.50 - - 1.00 - - str r7, [r1, r6]!
-# CHECK-NEXT: - 0.50 0.50 - - 1.00 - - str r7, [r1, r6, lsl #2]!
+# CHECK-NEXT: - - - - 1.00 1.00 - - str r7, [r1, r6, lsl #2]!
# CHECK-NEXT: - 0.50 0.50 - - 1.00 - - str r6, [sp, -r1]!
# CHECK-NEXT: - - - - 1.00 1.00 - - str r5, [r3], r9
# CHECK-NEXT: - - - - 1.00 1.00 - - str r4, [r2], -r5
More information about the llvm-commits
mailing list