[llvm] d3bcfe2 - AMDGPU: Implement getNoPreservedMask

[Matt Arsenault via llvm-commits]

Author: Matt Arsenault
Date: 2020-10-22T10:17:31-04:00
New Revision: d3bcfe2a3602e14606417d8bb9d6bbaf636d9a02

URL: https://github.com/llvm/llvm-project/commit/d3bcfe2a3602e14606417d8bb9d6bbaf636d9a02
DIFF: https://github.com/llvm/llvm-project/commit/d3bcfe2a3602e14606417d8bb9d6bbaf636d9a02.diff

LOG: AMDGPU: Implement getNoPreservedMask

We don't support funclets for exception handling and I hit this when
manually reducing MIR.

Added: 
    llvm/test/CodeGen/AMDGPU/return-with-successors.mir

Modified: 
    llvm/lib/Target/AMDGPU/AMDGPUCallingConv.td
    llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
    llvm/lib/Target/AMDGPU/SIRegisterInfo.h

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AMDGPU/AMDGPUCallingConv.td b/llvm/lib/Target/AMDGPU/AMDGPUCallingConv.td
index 7c83b6dcb44b9..5cbd65b95dff8 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUCallingConv.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPUCallingConv.td
@@ -125,6 +125,8 @@ def CSR_AMDGPU_HighRegs : CalleeSavedRegs<
   (add CSR_AMDGPU_VGPRs, CSR_AMDGPU_SGPRs_32_105)
 >;
 
+def CSR_AMDGPU_NoRegs : CalleeSavedRegs<(add)>;
+
 // Calling convention for leaf functions
 def CC_AMDGPU_Func : CallingConv<[
   CCIfByVal<CCPassByVal<4, 4>>,

diff  --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
index 6000c8a2a7fdc..216e00e56a05e 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -152,6 +152,10 @@ const uint32_t *SIRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
   }
 }
 
+const uint32_t *SIRegisterInfo::getNoPreservedMask() const {
+  return CSR_AMDGPU_NoRegs_RegMask;
+}
+
 Register SIRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
   const SIFrameLowering *TFI =
       MF.getSubtarget<GCNSubtarget>().getFrameLowering();

diff  --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
index 978361b1a271c..829656d4f0fc2 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
@@ -68,6 +68,7 @@ class SIRegisterInfo final : public AMDGPUGenRegisterInfo {
   const MCPhysReg *getCalleeSavedRegsViaCopy(const MachineFunction *MF) const;
   const uint32_t *getCallPreservedMask(const MachineFunction &MF,
                                        CallingConv::ID) const override;
+  const uint32_t *getNoPreservedMask() const override;
 
   // Stack access is very expensive. CSRs are also the high registers, and we
   // want to minimize the number of used registers.

diff  --git a/llvm/test/CodeGen/AMDGPU/return-with-successors.mir b/llvm/test/CodeGen/AMDGPU/return-with-successors.mir
new file mode 100644
index 0000000000000..00b1faca0e902
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/return-with-successors.mir
@@ -0,0 +1,44 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs -run-pass=liveintervals -o - %s | FileCheck %s
+# Test that getNoPreservedMask is implemented, which is called when
+# return blocks have successors.
+
+---
+name: endpgm_with_successors
+tracksRegLiveness: true
+body:             |
+  ; CHECK-LABEL: name: endpgm_with_successors
+  ; CHECK: bb.0:
+  ; CHECK:   successors: %bb.1(0x80000000)
+  ; CHECK:   S_ENDPGM 0
+  ; CHECK: bb.1:
+  ; CHECK:   S_NOP 0
+  bb.0:
+    successors: %bb.1
+    S_ENDPGM 0
+
+  bb.1:
+    S_NOP 0
+
+...
+
+---
+name: setpc_with_successors
+tracksRegLiveness: true
+body:             |
+  ; CHECK-LABEL: name: setpc_with_successors
+  ; CHECK: bb.0:
+  ; CHECK:   successors: %bb.1(0x80000000)
+  ; CHECK:   liveins: $sgpr30_sgpr31
+  ; CHECK:   S_SETPC_B64 $sgpr30_sgpr31
+  ; CHECK: bb.1:
+  ; CHECK:   S_NOP 0
+  bb.0:
+    liveins: $sgpr30_sgpr31
+    successors: %bb.1
+    S_SETPC_B64 $sgpr30_sgpr31
+
+  bb.1:
+    S_NOP 0
+
+...