[PATCH] D89957: [ARM][SchedModels] Let ldm* instruction scheduling use MCSchedPredicate

[Eugene Leviant via Phabricator via llvm-commits]

evgeny777 added inline comments.


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Comment at: llvm/test/tools/llvm-mca/ARM/cortex-a57-memory-instructions.s:255
 # CHECK-NEXT:  16     10    16.00   *                   ldm	r2, {r0, r1, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, sp, lr, pc}
-# CHECK-NEXT:  16     10    16.00   *                   ldm	r2, {r0, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, sp, lr, pc}
+# CHECK-NEXT:  32     11    16.00   *                   ldm	r2, {r0, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, sp, lr, pc}
 # CHECK-NEXT:  1      1     1.00           *            str	r8, [r12]
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Cortex-A57 ldm* scheduling seems to be broken in terms of number of uops for instructions having base reg in register list. Patch doesn't address this.


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  https://reviews.llvm.org/D89957/new/

https://reviews.llvm.org/D89957