[PATCH] D83210: [RISCV][NFC] Add more tests for 32-bit constant materialization
Luís Marques via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Oct 22 03:36:57 PDT 2020
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG89840380d56e: [RISCV][NFC] Add more tests for 32-bit constant materialization (authored by luismarques).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D83210/new/
https://reviews.llvm.org/D83210
Files:
llvm/test/CodeGen/RISCV/imm.ll
Index: llvm/test/CodeGen/RISCV/imm.ll
===================================================================
--- llvm/test/CodeGen/RISCV/imm.ll
+++ llvm/test/CodeGen/RISCV/imm.ll
@@ -105,6 +105,57 @@
ret i32 -65536 ; -0x10000
}
+; This can be materialized with ADDI+SLLI, improving compressibility.
+
+define signext i32 @imm_left_shifted_addi() nounwind {
+; RV32I-LABEL: imm_left_shifted_addi:
+; RV32I: # %bb.0:
+; RV32I-NEXT: lui a0, 32
+; RV32I-NEXT: addi a0, a0, -64
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: imm_left_shifted_addi:
+; RV64I: # %bb.0:
+; RV64I-NEXT: lui a0, 32
+; RV64I-NEXT: addiw a0, a0, -64
+; RV64I-NEXT: ret
+ ret i32 131008 ; 0x1FFC0
+}
+
+; This can be materialized with ADDI+SRLI, improving compressibility.
+
+define signext i32 @imm_right_shifted_addi() nounwind {
+; RV32I-LABEL: imm_right_shifted_addi:
+; RV32I: # %bb.0:
+; RV32I-NEXT: lui a0, 524288
+; RV32I-NEXT: addi a0, a0, -1
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: imm_right_shifted_addi:
+; RV64I: # %bb.0:
+; RV64I-NEXT: lui a0, 524288
+; RV64I-NEXT: addiw a0, a0, -1
+; RV64I-NEXT: ret
+ ret i32 2147483647 ; 0x7FFFFFFF
+}
+
+; This can be materialized with LUI+SRLI, improving compressibility.
+
+define signext i32 @imm_right_shifted_lui() nounwind {
+; RV32I-LABEL: imm_right_shifted_lui:
+; RV32I: # %bb.0:
+; RV32I-NEXT: lui a0, 56
+; RV32I-NEXT: addi a0, a0, 580
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: imm_right_shifted_lui:
+; RV64I: # %bb.0:
+; RV64I-NEXT: lui a0, 56
+; RV64I-NEXT: addiw a0, a0, 580
+; RV64I-NEXT: ret
+ ret i32 229956 ; 0x38244
+}
+
define i64 @imm64_1() nounwind {
; RV32I-LABEL: imm64_1:
; RV32I: # %bb.0:
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