[PATCH] D89820: [AArch64][GlobalISel] Split post-legalizer combiner to allow for lowering at -O0

[Jessica Paquette via Phabricator via llvm-commits]

paquette added inline comments.


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Comment at: llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp:503
+  GISelKnownBits *KB = &getAnalysis<GISelKnownBitsAnalysis>().get(MF);
+  MachineDominatorTree *MDT =
+      IsOptNone ? nullptr : &getAnalysis<MachineDominatorTree>();
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aemerson wrote:
> If this is a lowering pass then we may not need a dominator tree and thus IsOptNone variable plumbing through? If something needs to run only w/ optimizations that can live in the actual combiner pass.
Hm yeah, good point.

We might also not need known bits either?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D89820/new/

https://reviews.llvm.org/D89820