[llvm] bf9edcb - [ARM][SchedModels] Convert IsLdrAm3RegOffPred to MCSchedPredicate

[Evgeny Leviant via llvm-commits]

Author: Evgeny Leviant
Date: 2020-10-21T20:49:10+03:00
New Revision: bf9edcb6fda7e19487c2dca605a95e8a6779a80a

URL: https://github.com/llvm/llvm-project/commit/bf9edcb6fda7e19487c2dca605a95e8a6779a80a
DIFF: https://github.com/llvm/llvm-project/commit/bf9edcb6fda7e19487c2dca605a95e8a6779a80a.diff

LOG: [ARM][SchedModels] Convert IsLdrAm3RegOffPred to MCSchedPredicate

Differential revision: https://reviews.llvm.org/D89876

Added: 
    

Modified: 
    llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
    llvm/lib/Target/ARM/ARMBaseInstrInfo.h
    llvm/lib/Target/ARM/ARMScheduleA57.td
    llvm/test/tools/llvm-mca/ARM/cortex-a57-memory-instructions.s

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
index 3822f9057d94..0632e1be2fc9 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -612,12 +612,6 @@ bool ARMBaseInstrInfo::isCPSRDefined(const MachineInstr &MI) {
   return false;
 }
 
-bool ARMBaseInstrInfo::isAddrMode3OpImm(const MachineInstr &MI,
-                                        unsigned Op) const {
-  const MachineOperand &Offset = MI.getOperand(Op + 1);
-  return Offset.getReg() != 0;
-}
-
 // Load with negative register offset requires additional 1cyc and +I unit
 // for Cortex A57
 bool ARMBaseInstrInfo::isAddrMode3OpMinusReg(const MachineInstr &MI,

diff  --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
index f997322107af..f894a85c914f 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
@@ -178,7 +178,6 @@ class ARMBaseInstrInfo : public ARMGenInstrInfo {
 
   // CPSR defined in instruction
   static bool isCPSRDefined(const MachineInstr &MI);
-  bool isAddrMode3OpImm(const MachineInstr &MI, unsigned Op) const;
   bool isAddrMode3OpMinusReg(const MachineInstr &MI, unsigned Op) const;
 
   // Load, scaled register offset

diff  --git a/llvm/lib/Target/ARM/ARMScheduleA57.td b/llvm/lib/Target/ARM/ARMScheduleA57.td
index 3663b9d7d653..1a9de1d9fb78 100644
--- a/llvm/lib/Target/ARM/ARMScheduleA57.td
+++ b/llvm/lib/Target/ARM/ARMScheduleA57.td
@@ -28,14 +28,9 @@ def IsCPSRDefinedAndPredicatedPred :
 // Cortex A57 rev. r1p0 or later (false = r0px)
 def IsR1P0AndLaterPred : SchedPredicate<[{false}]>;
 
-// If Addrmode3 contains register offset (not immediate)
-def IsLdrAm3RegOffPred :
-  SchedPredicate<[{!TII->isAddrMode3OpImm(*MI, 1)}]>;
-// The same predicate with operand offset 2 and 3:
-def IsLdrAm3RegOffPredX2 :
-  SchedPredicate<[{!TII->isAddrMode3OpImm(*MI, 2)}]>;
-def IsLdrAm3RegOffPredX3 :
-  SchedPredicate<[{!TII->isAddrMode3OpImm(*MI, 3)}]>;
+def IsLdrAm3RegOffPred : MCSchedPredicate<CheckInvalidRegOperand<2>>;
+def IsLdrAm3RegOffPredX2 : MCSchedPredicate<CheckInvalidRegOperand<3>>;
+def IsLdrAm3RegOffPredX3 : MCSchedPredicate<CheckInvalidRegOperand<4>>;
 
 // If Addrmode3 contains "minus register"
 def IsLdrAm3NegRegOffPred :

diff  --git a/llvm/test/tools/llvm-mca/ARM/cortex-a57-memory-instructions.s b/llvm/test/tools/llvm-mca/ARM/cortex-a57-memory-instructions.s
index a0c99f77720e..96fd4206a41d 100644
--- a/llvm/test/tools/llvm-mca/ARM/cortex-a57-memory-instructions.s
+++ b/llvm/test/tools/llvm-mca/ARM/cortex-a57-memory-instructions.s
@@ -180,7 +180,7 @@
 # CHECK-NEXT:  2      4     1.00    *                   ldrbt	r1, [r2], -r6, lsl #12
 # CHECK-NEXT:  2      4     2.00    *                   ldrd	r0, r1, [r5]
 # CHECK-NEXT:  2      4     2.00    *                   ldrd	r8, r9, [r2, #15]
-# CHECK-NEXT:  4      4     2.00    *                   ldrd	r2, r3, [r9, #32]!
+# CHECK-NEXT:  4      5     2.00    *                   ldrd	r2, r3, [r9, #32]!
 # CHECK-NEXT:  4      4     2.00    *                   ldrd	r6, r7, [r1], #8
 # CHECK-NEXT:  4      4     2.00    *                   ldrd	r2, r3, [r8], #0
 # CHECK-NEXT:  4      4     2.00    *                   ldrd	r2, r3, [r8], #0