[PATCH] D89382: [SVE][CodeGen] Lower scalable integer vector reductions

[Kerry McLaughlin via Phabricator via llvm-commits]

kmclaughlin updated this revision to Diff 299730.
kmclaughlin added a comment.

- Changed getNode() to check if the operand type of vecreduce min/max is i1 instead of the result type
- Fixed a mistake with the changes to getNode() in the previous patch, where the transformations of [s|u]min & [s|u]max would also apply to other operations


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D89382/new/

https://reviews.llvm.org/D89382

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
  llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.h
  llvm/test/CodeGen/AArch64/sve-int-pred-reduce.ll
  llvm/test/CodeGen/AArch64/sve-int-reduce.ll
  llvm/test/CodeGen/AArch64/sve-split-int-pred-reduce.ll
  llvm/test/CodeGen/AArch64/sve-split-int-reduce.ll
  llvm/test/CodeGen/AArch64/vecreduce-umax-legalization.ll

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