[PATCH] D89876: [ARM][SchedModels] Convert IsLdrAm3RegOffPred to MCSchedPredicate

[Andrea Di Biagio via Phabricator via llvm-commits]

andreadb added a comment.

In D89876#2344978 <https://reviews.llvm.org/D89876#2344978>, @evgeny777 wrote:

> Addressed

Thanks!

I cannot comment on the mca numbers (I leave that part of the review to @dmgreen).
The changes to the predicates look good to me.

---

As a side note (unrelated to this patch):
If in future you plan to rewrite `isAddrMode3OpMinusReg`, then I suggest you to have a look at TIIPredicate.
Note also that `CheckImmOperand_s` can be used to define predicates like this:

  MyFunction(MI->getOperand(Index).getImm()) == Val

(see for example the code comments for `CheckOperandBase` in TargetInstrPredicate.td).


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