[PATCH] D89876: [ARM][SchedModels] Convert IsLdrAm3RegOffPred to MCSchedPredicate

[Eugene Leviant via Phabricator via llvm-commits]

evgeny777 updated this revision to Diff 299700.
evgeny777 retitled this revision from "[ARM][SchedModels] Convert few cortex-a57 predicates to MCSchedPredicate" to "[ARM][SchedModels] Convert IsLdrAm3RegOffPred  to MCSchedPredicate".
evgeny777 added a comment.

@andreadb Makes sense. Let's try AArch64-like approach for this case. I've updated patch to handle just `IsLdrAm3RegOffPred`


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D89876/new/

https://reviews.llvm.org/D89876

Files:
  llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
  llvm/lib/Target/ARM/ARMBaseInstrInfo.h
  llvm/lib/Target/ARM/ARMScheduleA57.td
  llvm/test/tools/llvm-mca/ARM/cortex-a57-memory-instructions.s


Index: llvm/test/tools/llvm-mca/ARM/cortex-a57-memory-instructions.s
===================================================================
--- llvm/test/tools/llvm-mca/ARM/cortex-a57-memory-instructions.s
+++ llvm/test/tools/llvm-mca/ARM/cortex-a57-memory-instructions.s
@@ -180,13 +180,13 @@
 # CHECK-NEXT:  2      4     1.00    *                   ldrbt	r1, [r2], -r6, lsl #12
 # CHECK-NEXT:  2      4     2.00    *                   ldrd	r0, r1, [r5]
 # CHECK-NEXT:  2      4     2.00    *                   ldrd	r8, r9, [r2, #15]
-# CHECK-NEXT:  4      4     2.00    *                   ldrd	r2, r3, [r9, #32]!
+# CHECK-NEXT:  4      5     2.00    *                   ldrd	r2, r3, [r9, #32]!
 # CHECK-NEXT:  4      4     2.00    *                   ldrd	r6, r7, [r1], #8
 # CHECK-NEXT:  4      4     2.00    *                   ldrd	r2, r3, [r8], #0
 # CHECK-NEXT:  4      4     2.00    *                   ldrd	r2, r3, [r8], #0
 # CHECK-NEXT:  4      4     2.00    *                   ldrd	r2, r3, [r8], #-0
 # CHECK-NEXT:  2      4     2.00    *                   ldrd	r4, r5, [r1, r3]
-# CHECK-NEXT:  4      4     2.00    *                   ldrd	r4, r5, [r7, r2]!
+# CHECK-NEXT:  4      5     2.00    *                   ldrd	r4, r5, [r7, r2]!
 # CHECK-NEXT:  4      4     2.00    *                   ldrd	r0, r1, [r8], r12
 # CHECK-NEXT:  4      4     2.00    *                   ldrd	r0, r1, [r8], -r12
 # CHECK-NEXT:  1      4     1.00    *                   ldrh	r3, [r4]
Index: llvm/lib/Target/ARM/ARMScheduleA57.td
===================================================================
--- llvm/lib/Target/ARM/ARMScheduleA57.td
+++ llvm/lib/Target/ARM/ARMScheduleA57.td
@@ -28,14 +28,9 @@
 // Cortex A57 rev. r1p0 or later (false = r0px)
 def IsR1P0AndLaterPred : SchedPredicate<[{false}]>;
 
-// If Addrmode3 contains register offset (not immediate)
-def IsLdrAm3RegOffPred :
-  SchedPredicate<[{!TII->isAddrMode3OpImm(*MI, 1)}]>;
-// The same predicate with operand offset 2 and 3:
-def IsLdrAm3RegOffPredX2 :
-  SchedPredicate<[{!TII->isAddrMode3OpImm(*MI, 2)}]>;
-def IsLdrAm3RegOffPredX3 :
-  SchedPredicate<[{!TII->isAddrMode3OpImm(*MI, 3)}]>;
+def IsLdrAm3RegOffPred : MCSchedPredicate<CheckIsRegOperand<2>>;
+def IsLdrAm3RegOffPredX2 : MCSchedPredicate<CheckIsRegOperand<3>>;
+def IsLdrAm3RegOffPredX3 : MCSchedPredicate<CheckIsRegOperand<4>>;
 
 // If Addrmode3 contains "minus register"
 def IsLdrAm3NegRegOffPred :
Index: llvm/lib/Target/ARM/ARMBaseInstrInfo.h
===================================================================
--- llvm/lib/Target/ARM/ARMBaseInstrInfo.h
+++ llvm/lib/Target/ARM/ARMBaseInstrInfo.h
@@ -178,7 +178,6 @@
 
   // CPSR defined in instruction
   static bool isCPSRDefined(const MachineInstr &MI);
-  bool isAddrMode3OpImm(const MachineInstr &MI, unsigned Op) const;
   bool isAddrMode3OpMinusReg(const MachineInstr &MI, unsigned Op) const;
 
   // Load, scaled register offset
Index: llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
===================================================================
--- llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -612,12 +612,6 @@
   return false;
 }
 
-bool ARMBaseInstrInfo::isAddrMode3OpImm(const MachineInstr &MI,
-                                        unsigned Op) const {
-  const MachineOperand &Offset = MI.getOperand(Op + 1);
-  return Offset.getReg() != 0;
-}
-
 // Load with negative register offset requires additional 1cyc and +I unit
 // for Cortex A57
 bool ARMBaseInstrInfo::isAddrMode3OpMinusReg(const MachineInstr &MI,


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