[PATCH] D89883: [ARM] Add a RegAllocHint for hinting t2DoLoopStart towards LR

[Dave Green via Phabricator via llvm-commits]

dmgreen created this revision.
dmgreen added reviewers: SjoerdMeijer, samparker, samtebbs, efriedma.
Herald added subscribers: danielkiss, hiraditya, kristof.beyls, tpr, qcolombet, MatzeB.
Herald added a project: LLVM.
dmgreen requested review of this revision.

This hints the operand of a t2DoLoopStart towards using LR, which can help make it more likely to become `t2DLS lr, lr`. This makes it easier to move if needed (as the input is the same as the output), or potentially remove entirely.

The hint is added after others (from COPY's etc) which still take precedence. It needed to find a place to add the hint, which currently uses the post isel custom inserter. The AMDGPU looks like it checks all the uses of the register in getRegAllocationHints, which sounds a little slower but may be preferable.


https://reviews.llvm.org/D89883

Files:
  llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
  llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
  llvm/lib/Target/ARM/ARMISelLowering.cpp
  llvm/lib/Target/ARM/ARMInstrThumb2.td
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/cond-vector-reduce-mve-codegen.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/exitcount.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/extending-loads.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/fast-fp-loops.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-guards.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-float-loops.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-tail-data-types.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/reductions.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/regalloc.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/remat-vctp.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/sibling-loops.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/tail-pred-disabled-in-loloops.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/tail-pred-intrinsic-round.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/tp-multiple-vpst.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/unpredload.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/vector-arith-codegen.ll
  llvm/test/CodeGen/Thumb2/mve-float16regloops.ll
  llvm/test/CodeGen/Thumb2/mve-float32regloops.ll
  llvm/test/CodeGen/Thumb2/mve-fma-loops.ll
  llvm/test/CodeGen/Thumb2/mve-fp16convertloops.ll
  llvm/test/CodeGen/Thumb2/mve-gather-ptrs.ll
  llvm/test/CodeGen/Thumb2/mve-gather-scatter-optimisation.ll
  llvm/test/CodeGen/Thumb2/mve-gather-scatter-ptr-address.ll
  llvm/test/CodeGen/Thumb2/mve-gather-scatter-tailpred.ll
  llvm/test/CodeGen/Thumb2/mve-postinc-distribute.ll
  llvm/test/CodeGen/Thumb2/mve-postinc-lsr.ll
  llvm/test/CodeGen/Thumb2/mve-pred-threshold.ll
  llvm/test/CodeGen/Thumb2/mve-pred-vctpvpsel.ll
  llvm/test/CodeGen/Thumb2/mve-satmul-loops.ll
  llvm/test/CodeGen/Thumb2/mve-shifts-scalar.ll
  llvm/test/CodeGen/Thumb2/mve-vecreduce-loops.ll
  llvm/test/CodeGen/Thumb2/mve-vldst4.ll
  llvm/test/Transforms/HardwareLoops/ARM/calls-codegen.ll
  llvm/test/Transforms/HardwareLoops/ARM/structure.ll

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