[llvm] 9fbb060 - [NFC][PowerPC]Add tests for folding RLWINM before and after RA.

[via llvm-commits]

Author: Esme-Yi
Date: 2020-10-21T06:38:22Z
New Revision: 9fbb060418e00ed7ee3cc88fdd9b90d78b2623a5

URL: https://github.com/llvm/llvm-project/commit/9fbb060418e00ed7ee3cc88fdd9b90d78b2623a5
DIFF: https://github.com/llvm/llvm-project/commit/9fbb060418e00ed7ee3cc88fdd9b90d78b2623a5.diff

LOG: [NFC][PowerPC]Add tests for folding RLWINM before and after RA.

Added: 
    

Modified: 
    llvm/test/CodeGen/PowerPC/fold-rlwinm.mir
    llvm/test/CodeGen/PowerPC/vsx_builtins.ll

Removed: 
    


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diff  --git a/llvm/test/CodeGen/PowerPC/fold-rlwinm.mir b/llvm/test/CodeGen/PowerPC/fold-rlwinm.mir
index ded5329a46cc..7a220964b0fd 100644
--- a/llvm/test/CodeGen/PowerPC/fold-rlwinm.mir
+++ b/llvm/test/CodeGen/PowerPC/fold-rlwinm.mir
@@ -182,3 +182,22 @@ body: |
     STW %2:gprc, %0:gprc, 100
     BLR8 implicit $lr8, implicit $rm
 ...
+---
+name: testFoldRLWINMAndANDI
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+    liveins: $x3
+    ; CHECK-LABEL: name: testFoldRLWINMAndANDI
+    ; CHECK: liveins: $x3
+    ; CHECK: [[COPY:%[0-9]+]]:g8rc = COPY $x3
+    ; CHECK: [[COPY1:%[0-9]+]]:gprc = COPY [[COPY]].sub_32
+    ; CHECK: [[RLWINM:%[0-9]+]]:gprc = RLWINM [[COPY1]], 4, 28, 31
+    ; CHECK: [[ANDI_rec:%[0-9]+]]:gprc = ANDI_rec [[RLWINM]], 4, implicit-def $cr0
+    ; CHECK: BLR8 implicit $lr8, implicit $rm
+    %0:g8rc = COPY $x3
+    %1:gprc = COPY %0.sub_32:g8rc
+    %2:gprc = RLWINM %1:gprc, 4, 28, 31
+    %3:gprc = ANDI_rec %2:gprc, 4, implicit-def $cr0
+    BLR8 implicit $lr8, implicit $rm
+...

diff  --git a/llvm/test/CodeGen/PowerPC/vsx_builtins.ll b/llvm/test/CodeGen/PowerPC/vsx_builtins.ll
index 2ab747384b69..0aae50af2649 100644
--- a/llvm/test/CodeGen/PowerPC/vsx_builtins.ll
+++ b/llvm/test/CodeGen/PowerPC/vsx_builtins.ll
@@ -106,3 +106,37 @@ define i32 @test_vec_test_swsqrts(<4 x float> %a) {
     ret i32 %0
 }
 declare i32 @llvm.ppc.vsx.xvtsqrtsp(<4 x float>)
+
+define i32 @xvtdivdp_andi(<2 x double> %a, <2 x double> %b) {
+; CHECK-LABEL: xvtdivdp_andi:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xvtdivdp cr0, v2, v3
+; CHECK-NEXT:    li r4, 222
+; CHECK-NEXT:    mfocrf r3, 128
+; CHECK-NEXT:    srwi r3, r3, 28
+; CHECK-NEXT:    andi. r3, r3, 2
+; CHECK-NEXT:    li r3, 22
+; CHECK-NEXT:    iseleq r3, r4, r3
+; CHECK-NEXT:    blr
+  entry:
+    %0 = tail call i32 @llvm.ppc.vsx.xvtdivdp(<2 x double> %a, <2 x double> %b)
+    %1 = and i32 %0, 2
+    %cmp.not = icmp eq i32 %1, 0
+    %retval.0 = select i1 %cmp.not, i32 222, i32 22
+    ret i32 %retval.0
+}
+
+define i32 @xvtdivdp_shift(<2 x double> %a, <2 x double> %b) {
+; CHECK-LABEL: xvtdivdp_shift:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xvtdivdp cr0, v2, v3
+; CHECK-NEXT:    mfocrf r3, 128
+; CHECK-NEXT:    srwi r3, r3, 28
+; CHECK-NEXT:    rlwinm r3, r3, 28, 31, 31
+; CHECK-NEXT:    blr
+entry:
+  %0 = tail call i32 @llvm.ppc.vsx.xvtdivdp(<2 x double> %a, <2 x double> %b)
+  %1 = lshr i32 %0, 4
+  %.lobit = and i32 %1, 1
+  ret i32 %.lobit
+}