[PATCH] D89788: [RISCV] Add GHC calling convention

[Andreas Schwab via Phabricator via llvm-commits]

schwab added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:1969
+  if (LocVT == MVT::i64) {
+    // Pass in STG registers: Base, Sp, Hp, R1, R2, R3, R4, R5, R6, R7, SpLim
+    static const MCPhysReg GPRList[] = {
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jrtc27 wrote:
> Do you have an explanation somewhere for why you've chosen these X and F registers for the calling convention? It'd also be useful to give their RISC-V ABI names here in the comments as the numbered registers aren't so easy to keep track of mentally.
I have just allocated the caller-saved registers in sequence s1 .. s11, fs0 .. fs11


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  https://reviews.llvm.org/D89788/new/

https://reviews.llvm.org/D89788