[llvm] bf540a6 - [InstCombine] Add (icmp ult (X + CA), C1) | (icmp eq X, C2) -> (icmp ule (X + CA), C1) test coverage

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2020-10-20T15:16:47+01:00
New Revision: bf540a64f3fc81cf0f14b5a15765f1ba9909d93e

URL: https://github.com/llvm/llvm-project/commit/bf540a64f3fc81cf0f14b5a15765f1ba9909d93e
DIFF: https://github.com/llvm/llvm-project/commit/bf540a64f3fc81cf0f14b5a15765f1ba9909d93e.diff

LOG: [InstCombine] Add (icmp ult (X + CA), C1) | (icmp eq X, C2) -> (icmp ule (X + CA), C1) test coverage

Add both commuted variants and vector uniform/nonuniform examples

Added: 
    

Modified: 
    llvm/test/Transforms/InstCombine/or.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/Transforms/InstCombine/or.ll b/llvm/test/Transforms/InstCombine/or.ll
index e13b5930a298..7e4115cc8934 100644
--- a/llvm/test/Transforms/InstCombine/or.ll
+++ b/llvm/test/Transforms/InstCombine/or.ll
@@ -376,6 +376,79 @@ define i1 @test36(i32 %x) {
   ret i1 %ret2
 }
 
+define i1 @test37(i32 %x) {
+; CHECK-LABEL: @test37(
+; CHECK-NEXT:    [[ADD1:%.*]] = add i32 [[X:%.*]], 7
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp ult i32 [[ADD1]], 31
+; CHECK-NEXT:    ret i1 [[TMP1]]
+;
+  %add1 = add i32 %x, 7
+  %cmp1 = icmp ult i32 %add1, 30
+  %cmp2 = icmp eq i32 %x, 23
+  %ret1 = or i1 %cmp1, %cmp2
+  ret i1 %ret1
+}
+
+define <2 x i1> @test37_uniform(<2 x i32> %x) {
+; CHECK-LABEL: @test37_uniform(
+; CHECK-NEXT:    [[ADD1:%.*]] = add <2 x i32> [[X:%.*]], <i32 7, i32 7>
+; CHECK-NEXT:    [[CMP1:%.*]] = icmp ult <2 x i32> [[ADD1]], <i32 30, i32 30>
+; CHECK-NEXT:    [[CMP2:%.*]] = icmp eq <2 x i32> [[X]], <i32 23, i32 23>
+; CHECK-NEXT:    [[RET1:%.*]] = or <2 x i1> [[CMP1]], [[CMP2]]
+; CHECK-NEXT:    ret <2 x i1> [[RET1]]
+;
+  %add1 = add <2 x i32> %x, <i32 7, i32 7>
+  %cmp1 = icmp ult <2 x i32> %add1, <i32 30, i32 30>
+  %cmp2 = icmp eq <2 x i32> %x, <i32 23, i32 23>
+  %ret1 = or <2 x i1> %cmp1, %cmp2
+  ret <2 x i1> %ret1
+}
+
+define <2 x i1> @test37_undef(<2 x i32> %x) {
+; CHECK-LABEL: @test37_undef(
+; CHECK-NEXT:    [[ADD1:%.*]] = add <2 x i32> [[X:%.*]], <i32 7, i32 undef>
+; CHECK-NEXT:    [[CMP1:%.*]] = icmp ult <2 x i32> [[ADD1]], <i32 30, i32 undef>
+; CHECK-NEXT:    [[CMP2:%.*]] = icmp eq <2 x i32> [[X]], <i32 23, i32 undef>
+; CHECK-NEXT:    [[RET1:%.*]] = or <2 x i1> [[CMP1]], [[CMP2]]
+; CHECK-NEXT:    ret <2 x i1> [[RET1]]
+;
+  %add1 = add <2 x i32> %x, <i32 7, i32 undef>
+  %cmp1 = icmp ult <2 x i32> %add1, <i32 30, i32 undef>
+  %cmp2 = icmp eq <2 x i32> %x, <i32 23, i32 undef>
+  %ret1 = or <2 x i1> %cmp1, %cmp2
+  ret <2 x i1> %ret1
+}
+
+define i1 @test38(i32 %x) {
+; CHECK-LABEL: @test38(
+; CHECK-NEXT:    [[ADD1:%.*]] = add i32 [[X:%.*]], 7
+; CHECK-NEXT:    [[CMP1:%.*]] = icmp eq i32 [[X]], 23
+; CHECK-NEXT:    [[CMP2:%.*]] = icmp ult i32 [[ADD1]], 30
+; CHECK-NEXT:    [[RET1:%.*]] = or i1 [[CMP1]], [[CMP2]]
+; CHECK-NEXT:    ret i1 [[RET1]]
+;
+  %add1 = add i32 %x, 7
+  %cmp1 = icmp eq i32 %x, 23
+  %cmp2 = icmp ult i32 %add1, 30
+  %ret1 = or i1 %cmp1, %cmp2
+  ret i1 %ret1
+}
+
+define <2 x i1> @test38_nonuniform(<2 x i32> %x) {
+; CHECK-LABEL: @test38_nonuniform(
+; CHECK-NEXT:    [[ADD1:%.*]] = add <2 x i32> [[X:%.*]], <i32 7, i32 24>
+; CHECK-NEXT:    [[CMP1:%.*]] = icmp eq <2 x i32> [[X]], <i32 23, i32 8>
+; CHECK-NEXT:    [[CMP2:%.*]] = icmp ult <2 x i32> [[ADD1]], <i32 30, i32 32>
+; CHECK-NEXT:    [[RET1:%.*]] = or <2 x i1> [[CMP1]], [[CMP2]]
+; CHECK-NEXT:    ret <2 x i1> [[RET1]]
+;
+  %add1 = add <2 x i32> %x, <i32 7, i32 24>
+  %cmp1 = icmp eq <2 x i32> %x, <i32 23, i32 8>
+  %cmp2 = icmp ult <2 x i32> %add1, <i32 30, i32 32>
+  %ret1 = or <2 x i1> %cmp1, %cmp2
+  ret <2 x i1> %ret1
+}
+
 define i32 @orsext_to_sel(i32 %x, i1 %y) {
 ; CHECK-LABEL: @orsext_to_sel(
 ; CHECK-NEXT:    [[OR:%.*]] = select i1 [[Y:%.*]], i32 -1, i32 [[X:%.*]]