[PATCH] D88572: AMDGPU/SelectionDAG Check for NaN, DX10Clamp and IEEE in fmed3 combine

[Petar Avramovic via Phabricator via llvm-commits]

Petar.Avramovic added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/SIISelLowering.cpp:9847
   // register pressure for no benefit.
 
   if (Opc != AMDGPUISD::FMIN_LEGACY && Opc != AMDGPUISD::FMAX_LEGACY &&
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This patch fixes clamp and fmed3 folds that could be incorrect with IEEE=true(potential not-silenced SNaN inputs).
@arsenm Folding ISD::FMAXNUM with IEEE=true into max3 here could be incorrect when one of the inputs is SNaN. There are no correctness issues with IEEE=false.
Thoughts on moving this combine after legalizer? We could also potentially move min3/max3 and min/max patterns with constants to td file so that global-isel can use them as well.


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  https://reviews.llvm.org/D88572/new/

https://reviews.llvm.org/D88572