[PATCH] D89610: AMDGPU: Fix missing read/writelane cases to skip with exec=0

[Jay Foad via Phabricator via llvm-commits]

foad added a comment.

In D89610#2339342 <https://reviews.llvm.org/D89610#2339342>, @nhaehnle wrote:

> In D89610#2339215 <https://reviews.llvm.org/D89610#2339215>, @arsenm wrote:
>
>> In D89610#2339205 <https://reviews.llvm.org/D89610#2339205>, @nhaehnle wrote:
>>
>>> Adding writelane absolutely makes sense to me, but:
>>>
>>>> Additionally, since we emit the final encoded instructions, this wasn't really matching readlane either.
>>>
>>> :(
>>>
>>> We have a bunch of places where we _always_ use real instructions, and presumably those are fine. But if we let real instructions creep into places where we usually use pseudos, we end up making the backend less efficient because over time, everybody will have to check for pseudos **and** reals (like in this particular case here). Can we instead add some sort of check that those real instructions aren't used during CodeGen? (The MI verifier should be able to check for this, for example.)
>>
>> There is some reason we use the encoded versions for readlane/writelane that I never remember what it is
>
> Would be good to understand that? A quick hack to replace the use of `TII->getMCOpcodeFromPseudo` from SIRegisterInfo.cpp shows a whole bunch of lit test changes, but so far the ones I've looked at are just scheduling changes that ought to be benign.

rG3db6ba8cfae254ecd3b5a8166d857cadb19d04e4 <https://reviews.llvm.org/rG3db6ba8cfae254ecd3b5a8166d857cadb19d04e4>.


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