[llvm] 991e861 - [ARM][SchedModels] Convert IsCPSRDefinedPred to MCSchedPredicate
Evgeny Leviant via llvm-commits
llvm-commits at lists.llvm.org
Tue Oct 20 01:15:08 PDT 2020
Author: Evgeny Leviant
Date: 2020-10-20T11:14:21+03:00
New Revision: 991e86156c88dfa64c908fe36da3a1945c3d2e50
URL: https://github.com/llvm/llvm-project/commit/991e86156c88dfa64c908fe36da3a1945c3d2e50
DIFF: https://github.com/llvm/llvm-project/commit/991e86156c88dfa64c908fe36da3a1945c3d2e50.diff
LOG: [ARM][SchedModels] Convert IsCPSRDefinedPred to MCSchedPredicate
Differential revision: https://reviews.llvm.org/D89460
Added:
Modified:
llvm/lib/Target/ARM/ARMSchedule.td
llvm/lib/Target/ARM/ARMScheduleA57.td
llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h
llvm/test/tools/llvm-mca/ARM/cortex-a57-basic-instructions.s
Removed:
################################################################################
diff --git a/llvm/lib/Target/ARM/ARMSchedule.td b/llvm/lib/Target/ARM/ARMSchedule.td
index f52c29707d41..8cdf12a625ce 100644
--- a/llvm/lib/Target/ARM/ARMSchedule.td
+++ b/llvm/lib/Target/ARM/ARMSchedule.td
@@ -157,6 +157,13 @@ def IsPredicated : CheckFunctionPredicateWithTII<
>;
def IsPredicatedPred : MCSchedPredicate<IsPredicated>;
+def IsCPSRDefined : CheckFunctionPredicateWithTII<
+ "ARM_MC::isCPSRDefined",
+ "ARMBaseInstrInfo::isCPSRDefined"
+>;
+
+def IsCPSRDefinedPred : MCSchedPredicate<IsCPSRDefined>;
+
//===----------------------------------------------------------------------===//
// Instruction Itinerary classes used for ARM
//
diff --git a/llvm/lib/Target/ARM/ARMScheduleA57.td b/llvm/lib/Target/ARM/ARMScheduleA57.td
index a52a2db3a0d6..3663b9d7d653 100644
--- a/llvm/lib/Target/ARM/ARMScheduleA57.td
+++ b/llvm/lib/Target/ARM/ARMScheduleA57.td
@@ -21,9 +21,9 @@
// Therefore, IssueWidth is set to the narrower of the two at three, while still
// modeling the machine as out-of-order.
-def IsCPSRDefinedPred : SchedPredicate<[{TII->isCPSRDefined(*MI)}]>;
+def IsCPSRDefinedAndPredicated : CheckAll<[IsCPSRDefined, IsPredicated]>;
def IsCPSRDefinedAndPredicatedPred :
- SchedPredicate<[{TII->isCPSRDefined(*MI) && TII->isPredicated(*MI)}]>;
+ MCSchedPredicate<IsCPSRDefinedAndPredicated>;
// Cortex A57 rev. r1p0 or later (false = r0px)
def IsR1P0AndLaterPred : SchedPredicate<[{false}]>;
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
index ced1c692141c..293c2d639f88 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
@@ -187,6 +187,17 @@ bool ARM_MC::isPredicated(const MCInst &MI, const MCInstrInfo *MCII) {
return PredOpIdx != -1 && MI.getOperand(PredOpIdx).getImm() != ARMCC::AL;
}
+bool ARM_MC::isCPSRDefined(const MCInst &MI, const MCInstrInfo *MCII) {
+ const MCInstrDesc &Desc = MCII->get(MI.getOpcode());
+ for (unsigned I = 0; I < MI.getNumOperands(); ++I) {
+ const MCOperand &MO = MI.getOperand(I);
+ if (MO.isReg() && MO.getReg() == ARM::CPSR &&
+ Desc.OpInfo[I].isOptionalDef())
+ return true;
+ }
+ return false;
+}
+
MCSubtargetInfo *ARM_MC::createARMMCSubtargetInfo(const Triple &TT,
StringRef CPU, StringRef FS) {
std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU);
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h
index b589c9fab8ce..31e58b4d24b2 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h
@@ -44,6 +44,7 @@ std::string ParseARMTriple(const Triple &TT, StringRef CPU);
void initLLVMToCVRegMapping(MCRegisterInfo *MRI);
bool isPredicated(const MCInst &MI, const MCInstrInfo *MCII);
+bool isCPSRDefined(const MCInst &MI, const MCInstrInfo *MCII);
/// Create a ARM MCSubtargetInfo instance. This is exposed so Asm parser, etc.
/// do not need to go through TargetRegistry.
diff --git a/llvm/test/tools/llvm-mca/ARM/cortex-a57-basic-instructions.s b/llvm/test/tools/llvm-mca/ARM/cortex-a57-basic-instructions.s
index 71b9e67ff481..acd0f7095f8e 100644
--- a/llvm/test/tools/llvm-mca/ARM/cortex-a57-basic-instructions.s
+++ b/llvm/test/tools/llvm-mca/ARM/cortex-a57-basic-instructions.s
@@ -1202,9 +1202,9 @@
# CHECK-NEXT: 1 1 0.50 mvn r5, r6, ror #6
# CHECK-NEXT: 1 1 0.50 mvn r5, r6, rrx
# CHECK-NEXT: 1 1 0.50 mvneq r2, r3
-# CHECK-NEXT: 1 1 0.50 mvnseq r2, r3, lsl #10
+# CHECK-NEXT: 1 2 1.00 mvnseq r2, r3, lsl #10
# CHECK-NEXT: 1 1 0.50 mvn r5, r6, lsl r7
-# CHECK-NEXT: 1 1 0.50 mvns r5, r6, lsr r7
+# CHECK-NEXT: 1 2 1.00 mvns r5, r6, lsr r7
# CHECK-NEXT: 1 2 0.50 mvngt r5, r6, asr r7
# CHECK-NEXT: 1 2 0.50 mvnslt r5, r6, ror r7
# CHECK-NEXT: 0 0 0.00 * * U nop
@@ -1356,10 +1356,10 @@
# CHECK-NEXT: 1 1 0.50 rrx sp, pc
# CHECK-NEXT: 1 1 0.50 rrx pc, lr
# CHECK-NEXT: 1 1 0.50 rrx lr, sp
-# CHECK-NEXT: 1 1 0.50 rrxs r0, r1
-# CHECK-NEXT: 1 1 0.50 rrxs sp, pc
-# CHECK-NEXT: 1 1 0.50 rrxs pc, lr
-# CHECK-NEXT: 1 1 0.50 rrxs lr, sp
+# CHECK-NEXT: 1 2 1.00 rrxs r0, r1
+# CHECK-NEXT: 1 2 1.00 rrxs sp, pc
+# CHECK-NEXT: 1 2 1.00 rrxs pc, lr
+# CHECK-NEXT: 1 2 1.00 rrxs lr, sp
# CHECK-NEXT: 2 2 1.00 * * U sadd16 r1, r2, r3
# CHECK-NEXT: 2 4 1.00 * * U sadd16gt r1, r2, r3
# CHECK-NEXT: 2 2 1.00 * * U sadd8 r1, r2, r3
@@ -1719,7 +1719,7 @@
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1.0] [1.1] [2] [3] [4] [5] [6]
-# CHECK-NEXT: 8.00 162.00 162.00 171.00 490.00 12.00 - -
+# CHECK-NEXT: 8.00 159.00 159.00 171.00 496.00 12.00 - -
# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1.0] [1.1] [2] [3] [4] [5] [6] Instructions:
@@ -2066,9 +2066,9 @@
# CHECK-NEXT: - 0.50 0.50 - - - - - mvn r5, r6, ror #6
# CHECK-NEXT: - 0.50 0.50 - - - - - mvn r5, r6, rrx
# CHECK-NEXT: - 0.50 0.50 - - - - - mvneq r2, r3
-# CHECK-NEXT: - 0.50 0.50 - - - - - mvnseq r2, r3, lsl #10
+# CHECK-NEXT: - - - - 1.00 - - - mvnseq r2, r3, lsl #10
# CHECK-NEXT: - 0.50 0.50 - - - - - mvn r5, r6, lsl r7
-# CHECK-NEXT: - 0.50 0.50 - - - - - mvns r5, r6, lsr r7
+# CHECK-NEXT: - - - - 1.00 - - - mvns r5, r6, lsr r7
# CHECK-NEXT: - 0.50 0.50 - - - - - mvngt r5, r6, asr r7
# CHECK-NEXT: - 0.50 0.50 - - - - - mvnslt r5, r6, ror r7
# CHECK-NEXT: - - - - - - - - nop
@@ -2220,10 +2220,10 @@
# CHECK-NEXT: - 0.50 0.50 - - - - - rrx sp, pc
# CHECK-NEXT: - 0.50 0.50 - - - - - rrx pc, lr
# CHECK-NEXT: - 0.50 0.50 - - - - - rrx lr, sp
-# CHECK-NEXT: - 0.50 0.50 - - - - - rrxs r0, r1
-# CHECK-NEXT: - 0.50 0.50 - - - - - rrxs sp, pc
-# CHECK-NEXT: - 0.50 0.50 - - - - - rrxs pc, lr
-# CHECK-NEXT: - 0.50 0.50 - - - - - rrxs lr, sp
+# CHECK-NEXT: - - - - 1.00 - - - rrxs r0, r1
+# CHECK-NEXT: - - - - 1.00 - - - rrxs sp, pc
+# CHECK-NEXT: - - - - 1.00 - - - rrxs pc, lr
+# CHECK-NEXT: - - - - 1.00 - - - rrxs lr, sp
# CHECK-NEXT: - 0.50 0.50 - 1.00 - - - sadd16 r1, r2, r3
# CHECK-NEXT: - 0.50 0.50 - 1.00 - - - sadd16gt r1, r2, r3
# CHECK-NEXT: - 0.50 0.50 - 1.00 - - - sadd8 r1, r2, r3
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