[llvm] 25955cb - [VE] Support br_cc comparing fp128
Kazushi Marukawa via llvm-commits
llvm-commits at lists.llvm.org
Mon Oct 19 02:29:47 PDT 2020
Author: Kazushi (Jam) Marukawa
Date: 2020-10-19T18:29:39+09:00
New Revision: 25955cbae4e2c60d9ecc6f40dc74abfb30af2573
URL: https://github.com/llvm/llvm-project/commit/25955cbae4e2c60d9ecc6f40dc74abfb30af2573
DIFF: https://github.com/llvm/llvm-project/commit/25955cbae4e2c60d9ecc6f40dc74abfb30af2573.diff
LOG: [VE] Support br_cc comparing fp128
Support br_cc instruction comparing fp128 values. Add a br_cc.ll
regression test for all kind of br_cc instructions. And, clean
existing branch regression tests, this time. Clean a brcond.ll
regression test for brcond instruction. Remove mixed branch1.ll
regression test.
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D89627
Added:
llvm/test/CodeGen/VE/br_cc.ll
Modified:
llvm/lib/Target/VE/VEInstrInfo.td
llvm/test/CodeGen/VE/brcond.ll
Removed:
llvm/test/CodeGen/VE/branch1.ll
################################################################################
diff --git a/llvm/lib/Target/VE/VEInstrInfo.td b/llvm/lib/Target/VE/VEInstrInfo.td
index 53924395375c..b9d8a9b0297a 100644
--- a/llvm/lib/Target/VE/VEInstrInfo.td
+++ b/llvm/lib/Target/VE/VEInstrInfo.td
@@ -1717,6 +1717,8 @@ multiclass BRCCFm<ValueType ty, SDPatternOperator BrOpNode1,
}
defm : BRCCFm<f32, BRCFSrr, BRCFSir>;
defm : BRCCFm<f64, BRCFDrr, BRCFDir>;
+def : Pat<(brcc cond:$cond, f128:$l, f128:$r, bb:$addr),
+ (BRCFDir (fcond2cc $cond), 0, (FCMPQrr $r, $l), bb:$addr)>;
//===----------------------------------------------------------------------===//
// Pseudo Instructions
diff --git a/llvm/test/CodeGen/VE/br_cc.ll b/llvm/test/CodeGen/VE/br_cc.ll
new file mode 100644
index 000000000000..e85069927abe
--- /dev/null
+++ b/llvm/test/CodeGen/VE/br_cc.ll
@@ -0,0 +1,986 @@
+; RUN: llc < %s -mtriple=ve | FileCheck %s
+
+; Function Attrs: nounwind
+define void @br_cc_i1_var(i1 zeroext %0, i1 zeroext %1) {
+; CHECK-LABEL: br_cc_i1_var:
+; CHECK: .LBB{{[0-9]+}}_4:
+; CHECK-NEXT: xor %s0, %s0, %s1
+; CHECK-NEXT: brne.w 0, %s0, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: #APP
+; CHECK-NEXT: nop
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: or %s11, 0, %s9
+ %3 = xor i1 %0, %1
+ br i1 %3, label %5, label %4
+
+4: ; preds = %2
+ tail call void asm sideeffect "nop", ""()
+ br label %5
+
+5: ; preds = %4, %2
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @br_cc_i8_var(i8 signext %0, i8 signext %1) {
+; CHECK-LABEL: br_cc_i8_var:
+; CHECK: .LBB{{[0-9]+}}_4:
+; CHECK-NEXT: brne.w %s0, %s1, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: #APP
+; CHECK-NEXT: nop
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: or %s11, 0, %s9
+ %3 = icmp eq i8 %0, %1
+ br i1 %3, label %4, label %5
+
+4: ; preds = %2
+ tail call void asm sideeffect "nop", ""()
+ br label %5
+
+5: ; preds = %4, %2
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @br_cc_u8_var(i8 zeroext %0, i8 zeroext %1) {
+; CHECK-LABEL: br_cc_u8_var:
+; CHECK: .LBB{{[0-9]+}}_4:
+; CHECK-NEXT: brne.w %s0, %s1, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: #APP
+; CHECK-NEXT: nop
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: or %s11, 0, %s9
+ %3 = icmp eq i8 %0, %1
+ br i1 %3, label %4, label %5
+
+4: ; preds = %2
+ tail call void asm sideeffect "nop", ""()
+ br label %5
+
+5: ; preds = %4, %2
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @br_cc_i16_var(i16 signext %0, i16 signext %1) {
+; CHECK-LABEL: br_cc_i16_var:
+; CHECK: .LBB{{[0-9]+}}_4:
+; CHECK-NEXT: brne.w %s0, %s1, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: #APP
+; CHECK-NEXT: nop
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: or %s11, 0, %s9
+ %3 = icmp eq i16 %0, %1
+ br i1 %3, label %4, label %5
+
+4: ; preds = %2
+ tail call void asm sideeffect "nop", ""()
+ br label %5
+
+5: ; preds = %4, %2
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @br_cc_u16_var(i16 zeroext %0, i16 zeroext %1) {
+; CHECK-LABEL: br_cc_u16_var:
+; CHECK: .LBB{{[0-9]+}}_4:
+; CHECK-NEXT: brne.w %s0, %s1, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: #APP
+; CHECK-NEXT: nop
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: or %s11, 0, %s9
+ %3 = icmp eq i16 %0, %1
+ br i1 %3, label %4, label %5
+
+4: ; preds = %2
+ tail call void asm sideeffect "nop", ""()
+ br label %5
+
+5: ; preds = %4, %2
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @br_cc_i32_var(i32 signext %0, i32 signext %1) {
+; CHECK-LABEL: br_cc_i32_var:
+; CHECK: .LBB{{[0-9]+}}_4:
+; CHECK-NEXT: brne.w %s0, %s1, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: #APP
+; CHECK-NEXT: nop
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: or %s11, 0, %s9
+ %3 = icmp eq i32 %0, %1
+ br i1 %3, label %4, label %5
+
+4: ; preds = %2
+ tail call void asm sideeffect "nop", ""()
+ br label %5
+
+5: ; preds = %4, %2
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @br_cc_u32_var(i32 zeroext %0, i32 zeroext %1) {
+; CHECK-LABEL: br_cc_u32_var:
+; CHECK: .LBB{{[0-9]+}}_4:
+; CHECK-NEXT: brne.w %s0, %s1, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: #APP
+; CHECK-NEXT: nop
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: or %s11, 0, %s9
+ %3 = icmp eq i32 %0, %1
+ br i1 %3, label %4, label %5
+
+4: ; preds = %2
+ tail call void asm sideeffect "nop", ""()
+ br label %5
+
+5: ; preds = %4, %2
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @br_cc_i64_var(i64 %0, i64 %1) {
+; CHECK-LABEL: br_cc_i64_var:
+; CHECK: .LBB{{[0-9]+}}_4:
+; CHECK-NEXT: brne.l %s0, %s1, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: #APP
+; CHECK-NEXT: nop
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: or %s11, 0, %s9
+ %3 = icmp eq i64 %0, %1
+ br i1 %3, label %4, label %5
+
+4: ; preds = %2
+ tail call void asm sideeffect "nop", ""()
+ br label %5
+
+5: ; preds = %4, %2
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @br_cc_u64_var(i64 %0, i64 %1) {
+; CHECK-LABEL: br_cc_u64_var:
+; CHECK: .LBB{{[0-9]+}}_4:
+; CHECK-NEXT: brne.l %s0, %s1, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: #APP
+; CHECK-NEXT: nop
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: or %s11, 0, %s9
+ %3 = icmp eq i64 %0, %1
+ br i1 %3, label %4, label %5
+
+4: ; preds = %2
+ tail call void asm sideeffect "nop", ""()
+ br label %5
+
+5: ; preds = %4, %2
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @br_cc_i128_var(i128 %0, i128 %1) {
+; CHECK-LABEL: br_cc_i128_var:
+; CHECK: .LBB{{[0-9]+}}_4:
+; CHECK-NEXT: xor %s1, %s1, %s3
+; CHECK-NEXT: xor %s0, %s0, %s2
+; CHECK-NEXT: or %s0, %s0, %s1
+; CHECK-NEXT: brne.l 0, %s0, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: #APP
+; CHECK-NEXT: nop
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: or %s11, 0, %s9
+ %3 = icmp eq i128 %0, %1
+ br i1 %3, label %4, label %5
+
+4: ; preds = %2
+ tail call void asm sideeffect "nop", ""()
+ br label %5
+
+5: ; preds = %4, %2
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @br_cc_u128_var(i128 %0, i128 %1) {
+; CHECK-LABEL: br_cc_u128_var:
+; CHECK: .LBB{{[0-9]+}}_4:
+; CHECK-NEXT: xor %s1, %s1, %s3
+; CHECK-NEXT: xor %s0, %s0, %s2
+; CHECK-NEXT: or %s0, %s0, %s1
+; CHECK-NEXT: brne.l 0, %s0, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: #APP
+; CHECK-NEXT: nop
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: or %s11, 0, %s9
+ %3 = icmp eq i128 %0, %1
+ br i1 %3, label %4, label %5
+
+4: ; preds = %2
+ tail call void asm sideeffect "nop", ""()
+ br label %5
+
+5: ; preds = %4, %2
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @br_cc_float_var(float %0, float %1) {
+; CHECK-LABEL: br_cc_float_var:
+; CHECK: .LBB{{[0-9]+}}_4:
+; CHECK-NEXT: brne.s %s0, %s1, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: #APP
+; CHECK-NEXT: nop
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: or %s11, 0, %s9
+ %3 = fcmp fast oeq float %0, %1
+ br i1 %3, label %4, label %5
+
+4: ; preds = %2
+ tail call void asm sideeffect "nop", ""()
+ br label %5
+
+5: ; preds = %4, %2
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @br_cc_double_var(double %0, double %1) {
+; CHECK-LABEL: br_cc_double_var:
+; CHECK: .LBB{{[0-9]+}}_4:
+; CHECK-NEXT: brne.d %s0, %s1, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: #APP
+; CHECK-NEXT: nop
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: or %s11, 0, %s9
+ %3 = fcmp fast oeq double %0, %1
+ br i1 %3, label %4, label %5
+
+4: ; preds = %2
+ tail call void asm sideeffect "nop", ""()
+ br label %5
+
+5: ; preds = %4, %2
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @br_cc_quad_var(fp128 %0, fp128 %1) {
+; CHECK-LABEL: br_cc_quad_var:
+; CHECK: .LBB{{[0-9]+}}_4:
+; CHECK-NEXT: fcmp.q %s0, %s2, %s0
+; CHECK-NEXT: brne.d 0, %s0, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: #APP
+; CHECK-NEXT: nop
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: or %s11, 0, %s9
+ %3 = fcmp fast oeq fp128 %0, %1
+ br i1 %3, label %4, label %5
+
+4: ; preds = %2
+ tail call void asm sideeffect "nop", ""()
+ br label %5
+
+5: ; preds = %4, %2
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @br_cc_i1_imm(i1 zeroext %0) {
+; CHECK-LABEL: br_cc_i1_imm:
+; CHECK: .LBB{{[0-9]+}}_4:
+; CHECK-NEXT: brne.w 0, %s0, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: #APP
+; CHECK-NEXT: nop
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: or %s11, 0, %s9
+ br i1 %0, label %3, label %2
+
+2: ; preds = %1
+ tail call void asm sideeffect "nop", ""()
+ br label %3
+
+3: ; preds = %2, %1
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @br_cc_i8_imm(i8 signext %0) {
+; CHECK-LABEL: br_cc_i8_imm:
+; CHECK: .LBB{{[0-9]+}}_4:
+; CHECK-NEXT: brlt.w -10, %s0, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: #APP
+; CHECK-NEXT: nop
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: or %s11, 0, %s9
+ %2 = icmp slt i8 %0, -9
+ br i1 %2, label %3, label %4
+
+3: ; preds = %1
+ tail call void asm sideeffect "nop", ""()
+ br label %4
+
+4: ; preds = %3, %1
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @br_cc_u8_imm(i8 zeroext %0) {
+; CHECK-LABEL: br_cc_u8_imm:
+; CHECK: .LBB{{[0-9]+}}_4:
+; CHECK-NEXT: cmpu.w %s0, 8, %s0
+; CHECK-NEXT: brgt.w 0, %s0, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: #APP
+; CHECK-NEXT: nop
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: or %s11, 0, %s9
+ %2 = icmp ult i8 %0, 9
+ br i1 %2, label %3, label %4
+
+3: ; preds = %1
+ tail call void asm sideeffect "nop", ""()
+ br label %4
+
+4: ; preds = %3, %1
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @br_cc_i16_imm(i16 signext %0) {
+; CHECK-LABEL: br_cc_i16_imm:
+; CHECK: .LBB{{[0-9]+}}_4:
+; CHECK-NEXT: brlt.w 62, %s0, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: #APP
+; CHECK-NEXT: nop
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: or %s11, 0, %s9
+ %2 = icmp slt i16 %0, 63
+ br i1 %2, label %3, label %4
+
+3: ; preds = %1
+ tail call void asm sideeffect "nop", ""()
+ br label %4
+
+4: ; preds = %3, %1
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @br_cc_u16_imm(i16 zeroext %0) {
+; CHECK-LABEL: br_cc_u16_imm:
+; CHECK: .LBB{{[0-9]+}}_4:
+; CHECK-NEXT: cmpu.w %s0, 63, %s0
+; CHECK-NEXT: brgt.w 0, %s0, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: #APP
+; CHECK-NEXT: nop
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: or %s11, 0, %s9
+ %2 = icmp ult i16 %0, 64
+ br i1 %2, label %3, label %4
+
+3: ; preds = %1
+ tail call void asm sideeffect "nop", ""()
+ br label %4
+
+4: ; preds = %3, %1
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @br_cc_i32_imm(i32 signext %0) {
+; CHECK-LABEL: br_cc_i32_imm:
+; CHECK: .LBB{{[0-9]+}}_4:
+; CHECK-NEXT: brlt.w 63, %s0, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: #APP
+; CHECK-NEXT: nop
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: or %s11, 0, %s9
+ %2 = icmp slt i32 %0, 64
+ br i1 %2, label %3, label %4
+
+3: ; preds = %1
+ tail call void asm sideeffect "nop", ""()
+ br label %4
+
+4: ; preds = %3, %1
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @br_cc_u32_imm(i32 zeroext %0) {
+; CHECK-LABEL: br_cc_u32_imm:
+; CHECK: .LBB{{[0-9]+}}_4:
+; CHECK-NEXT: cmpu.w %s0, 63, %s0
+; CHECK-NEXT: brgt.w 0, %s0, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: #APP
+; CHECK-NEXT: nop
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: or %s11, 0, %s9
+ %2 = icmp ult i32 %0, 64
+ br i1 %2, label %3, label %4
+
+3: ; preds = %1
+ tail call void asm sideeffect "nop", ""()
+ br label %4
+
+4: ; preds = %3, %1
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @br_cc_i64_imm(i64 %0) {
+; CHECK-LABEL: br_cc_i64_imm:
+; CHECK: .LBB{{[0-9]+}}_4:
+; CHECK-NEXT: brlt.l 63, %s0, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: #APP
+; CHECK-NEXT: nop
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: or %s11, 0, %s9
+ %2 = icmp slt i64 %0, 64
+ br i1 %2, label %3, label %4
+
+3: ; preds = %1
+ tail call void asm sideeffect "nop", ""()
+ br label %4
+
+4: ; preds = %3, %1
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @br_cc_u64_imm(i64 %0) {
+; CHECK-LABEL: br_cc_u64_imm:
+; CHECK: .LBB{{[0-9]+}}_4:
+; CHECK-NEXT: cmpu.l %s0, 63, %s0
+; CHECK-NEXT: brgt.l 0, %s0, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: #APP
+; CHECK-NEXT: nop
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: or %s11, 0, %s9
+ %2 = icmp ult i64 %0, 64
+ br i1 %2, label %3, label %4
+
+3: ; preds = %1
+ tail call void asm sideeffect "nop", ""()
+ br label %4
+
+4: ; preds = %3, %1
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @br_cc_i128_imm(i128 %0) {
+; CHECK-LABEL: br_cc_i128_imm:
+; CHECK: .LBB{{[0-9]+}}_4:
+; CHECK-NEXT: or %s2, 0, (0)1
+; CHECK-NEXT: cmps.l %s1, %s1, %s2
+; CHECK-NEXT: or %s3, 0, %s2
+; CHECK-NEXT: cmov.l.gt %s3, (63)0, %s1
+; CHECK-NEXT: or %s4, 63, (0)1
+; CHECK-NEXT: cmpu.l %s0, %s0, %s4
+; CHECK-NEXT: cmov.l.gt %s2, (63)0, %s0
+; CHECK-NEXT: cmov.l.eq %s3, %s2, %s1
+; CHECK-NEXT: brne.w 0, %s3, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: #APP
+; CHECK-NEXT: nop
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: or %s11, 0, %s9
+ %2 = icmp slt i128 %0, 64
+ br i1 %2, label %3, label %4
+
+3: ; preds = %1
+ tail call void asm sideeffect "nop", ""()
+ br label %4
+
+4: ; preds = %3, %1
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @br_cc_u128_imm(i128 %0) {
+; CHECK-LABEL: br_cc_u128_imm:
+; CHECK: .LBB{{[0-9]+}}_4:
+; CHECK-NEXT: or %s2, 0, (0)1
+; CHECK-NEXT: cmps.l %s1, %s1, %s2
+; CHECK-NEXT: or %s3, 0, %s2
+; CHECK-NEXT: cmov.l.ne %s3, (63)0, %s1
+; CHECK-NEXT: or %s4, 63, (0)1
+; CHECK-NEXT: cmpu.l %s0, %s0, %s4
+; CHECK-NEXT: cmov.l.gt %s2, (63)0, %s0
+; CHECK-NEXT: cmov.l.eq %s3, %s2, %s1
+; CHECK-NEXT: brne.w 0, %s3, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: #APP
+; CHECK-NEXT: nop
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: or %s11, 0, %s9
+ %2 = icmp ult i128 %0, 64
+ br i1 %2, label %3, label %4
+
+3: ; preds = %1
+ tail call void asm sideeffect "nop", ""()
+ br label %4
+
+4: ; preds = %3, %1
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @br_cc_float_imm(float %0) {
+; CHECK-LABEL: br_cc_float_imm:
+; CHECK: .LBB{{[0-9]+}}_4:
+; CHECK-NEXT: brle.s 0, %s0, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: #APP
+; CHECK-NEXT: nop
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: or %s11, 0, %s9
+ %2 = fcmp fast olt float %0, 0.000000e+00
+ br i1 %2, label %3, label %4
+
+3: ; preds = %1
+ tail call void asm sideeffect "nop", ""()
+ br label %4
+
+4: ; preds = %3, %1
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @br_cc_double_imm(double %0) {
+; CHECK-LABEL: br_cc_double_imm:
+; CHECK: .LBB{{[0-9]+}}_4:
+; CHECK-NEXT: brle.d 0, %s0, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: #APP
+; CHECK-NEXT: nop
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: or %s11, 0, %s9
+ %2 = fcmp fast olt double %0, 0.000000e+00
+ br i1 %2, label %3, label %4
+
+3: ; preds = %1
+ tail call void asm sideeffect "nop", ""()
+ br label %4
+
+4: ; preds = %3, %1
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @br_cc_quad_imm(fp128 %0) {
+; CHECK-LABEL: br_cc_quad_imm:
+; CHECK: .LBB{{[0-9]+}}_4:
+; CHECK-NEXT: lea %s2, .LCPI{{[0-9]+}}_0 at lo
+; CHECK-NEXT: and %s2, %s2, (32)0
+; CHECK-NEXT: lea.sl %s2, .LCPI{{[0-9]+}}_0 at hi(, %s2)
+; CHECK-NEXT: ld %s4, 8(, %s2)
+; CHECK-NEXT: ld %s5, (, %s2)
+; CHECK-NEXT: fcmp.q %s0, %s4, %s0
+; CHECK-NEXT: brge.d 0, %s0, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: #APP
+; CHECK-NEXT: nop
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: or %s11, 0, %s9
+ %2 = fcmp fast olt fp128 %0, 0xL00000000000000000000000000000000
+ br i1 %2, label %3, label %4
+
+3: ; preds = %1
+ tail call void asm sideeffect "nop", ""()
+ br label %4
+
+4: ; preds = %3, %1
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @br_cc_imm_i1(i1 zeroext %0) {
+; CHECK-LABEL: br_cc_imm_i1:
+; CHECK: .LBB{{[0-9]+}}_4:
+; CHECK-NEXT: breq.w 0, %s0, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: #APP
+; CHECK-NEXT: nop
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: or %s11, 0, %s9
+ br i1 %0, label %2, label %3
+
+2: ; preds = %1
+ tail call void asm sideeffect "nop", ""()
+ br label %3
+
+3: ; preds = %2, %1
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @br_cc_imm_i8(i8 signext %0) {
+; CHECK-LABEL: br_cc_imm_i8:
+; CHECK: .LBB{{[0-9]+}}_4:
+; CHECK-NEXT: brgt.w -9, %s0, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: #APP
+; CHECK-NEXT: nop
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: or %s11, 0, %s9
+ %2 = icmp sgt i8 %0, -10
+ br i1 %2, label %3, label %4
+
+3: ; preds = %1
+ tail call void asm sideeffect "nop", ""()
+ br label %4
+
+4: ; preds = %3, %1
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @br_cc_imm_u8(i8 zeroext %0) {
+; CHECK-LABEL: br_cc_imm_u8:
+; CHECK: .LBB{{[0-9]+}}_4:
+; CHECK-NEXT: cmpu.w %s0, 9, %s0
+; CHECK-NEXT: brlt.w 0, %s0, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: #APP
+; CHECK-NEXT: nop
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: or %s11, 0, %s9
+ %2 = icmp ugt i8 %0, 8
+ br i1 %2, label %3, label %4
+
+3: ; preds = %1
+ tail call void asm sideeffect "nop", ""()
+ br label %4
+
+4: ; preds = %3, %1
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @br_cc_imm_i16(i16 signext %0) {
+; CHECK-LABEL: br_cc_imm_i16:
+; CHECK: .LBB{{[0-9]+}}_4:
+; CHECK-NEXT: brgt.w 63, %s0, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: #APP
+; CHECK-NEXT: nop
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: or %s11, 0, %s9
+ %2 = icmp sgt i16 %0, 62
+ br i1 %2, label %3, label %4
+
+3: ; preds = %1
+ tail call void asm sideeffect "nop", ""()
+ br label %4
+
+4: ; preds = %3, %1
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @br_cc_imm_u16(i16 zeroext %0) {
+; CHECK-LABEL: br_cc_imm_u16:
+; CHECK: .LBB{{[0-9]+}}_4:
+; CHECK-NEXT: lea %s1, 64
+; CHECK-NEXT: cmpu.w %s0, %s1, %s0
+; CHECK-NEXT: brlt.w 0, %s0, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: #APP
+; CHECK-NEXT: nop
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: or %s11, 0, %s9
+ %2 = icmp ugt i16 %0, 63
+ br i1 %2, label %3, label %4
+
+3: ; preds = %1
+ tail call void asm sideeffect "nop", ""()
+ br label %4
+
+4: ; preds = %3, %1
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @br_cc_imm_i32(i32 signext %0) {
+; CHECK-LABEL: br_cc_imm_i32:
+; CHECK: .LBB{{[0-9]+}}_4:
+; CHECK-NEXT: brgt.w -64, %s0, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: #APP
+; CHECK-NEXT: nop
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: or %s11, 0, %s9
+ %2 = icmp sgt i32 %0, -65
+ br i1 %2, label %3, label %4
+
+3: ; preds = %1
+ tail call void asm sideeffect "nop", ""()
+ br label %4
+
+4: ; preds = %3, %1
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @br_cc_imm_u32(i32 zeroext %0) {
+; CHECK-LABEL: br_cc_imm_u32:
+; CHECK: .LBB{{[0-9]+}}_4:
+; CHECK-NEXT: cmpu.w %s0, -64, %s0
+; CHECK-NEXT: brlt.w 0, %s0, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: #APP
+; CHECK-NEXT: nop
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: or %s11, 0, %s9
+ %2 = icmp ugt i32 %0, -65
+ br i1 %2, label %3, label %4
+
+3: ; preds = %1
+ tail call void asm sideeffect "nop", ""()
+ br label %4
+
+4: ; preds = %3, %1
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @br_cc_imm_i64(i64 %0) {
+; CHECK-LABEL: br_cc_imm_i64:
+; CHECK: .LBB{{[0-9]+}}_4:
+; CHECK-NEXT: brgt.l -64, %s0, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: #APP
+; CHECK-NEXT: nop
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: or %s11, 0, %s9
+ %2 = icmp sgt i64 %0, -65
+ br i1 %2, label %3, label %4
+
+3: ; preds = %1
+ tail call void asm sideeffect "nop", ""()
+ br label %4
+
+4: ; preds = %3, %1
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @br_cc_imm_u64(i64 %0) {
+; CHECK-LABEL: br_cc_imm_u64:
+; CHECK: .LBB{{[0-9]+}}_4:
+; CHECK-NEXT: cmpu.l %s0, -64, %s0
+; CHECK-NEXT: brlt.l 0, %s0, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: #APP
+; CHECK-NEXT: nop
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: or %s11, 0, %s9
+ %2 = icmp ugt i64 %0, -65
+ br i1 %2, label %3, label %4
+
+3: ; preds = %1
+ tail call void asm sideeffect "nop", ""()
+ br label %4
+
+4: ; preds = %3, %1
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @br_cc_imm_i128(i128 %0) {
+; CHECK-LABEL: br_cc_imm_i128:
+; CHECK: .LBB{{[0-9]+}}_4:
+; CHECK-NEXT: or %s2, -1, (0)1
+; CHECK-NEXT: or %s3, 0, (0)1
+; CHECK-NEXT: cmps.l %s1, %s1, %s2
+; CHECK-NEXT: or %s2, 0, %s3
+; CHECK-NEXT: cmov.l.lt %s2, (63)0, %s1
+; CHECK-NEXT: or %s4, -64, (0)1
+; CHECK-NEXT: cmpu.l %s0, %s0, %s4
+; CHECK-NEXT: cmov.l.lt %s3, (63)0, %s0
+; CHECK-NEXT: cmov.l.eq %s2, %s3, %s1
+; CHECK-NEXT: brne.w 0, %s2, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: #APP
+; CHECK-NEXT: nop
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: or %s11, 0, %s9
+ %2 = icmp sgt i128 %0, -65
+ br i1 %2, label %3, label %4
+
+3: ; preds = %1
+ tail call void asm sideeffect "nop", ""()
+ br label %4
+
+4: ; preds = %3, %1
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @br_cc_imm_u128(i128 %0) {
+; CHECK-LABEL: br_cc_imm_u128:
+; CHECK: .LBB{{[0-9]+}}_4:
+; CHECK-NEXT: or %s2, -1, (0)1
+; CHECK-NEXT: or %s3, 0, (0)1
+; CHECK-NEXT: cmps.l %s1, %s1, %s2
+; CHECK-NEXT: or %s2, 0, %s3
+; CHECK-NEXT: cmov.l.ne %s2, (63)0, %s1
+; CHECK-NEXT: or %s4, -64, (0)1
+; CHECK-NEXT: cmpu.l %s0, %s0, %s4
+; CHECK-NEXT: cmov.l.lt %s3, (63)0, %s0
+; CHECK-NEXT: cmov.l.eq %s2, %s3, %s1
+; CHECK-NEXT: brne.w 0, %s2, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: #APP
+; CHECK-NEXT: nop
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: or %s11, 0, %s9
+ %2 = icmp ugt i128 %0, -65
+ br i1 %2, label %3, label %4
+
+3: ; preds = %1
+ tail call void asm sideeffect "nop", ""()
+ br label %4
+
+4: ; preds = %3, %1
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @br_cc_imm_float(float %0) {
+; CHECK-LABEL: br_cc_imm_float:
+; CHECK: .LBB{{[0-9]+}}_4:
+; CHECK-NEXT: brgt.s 0, %s0, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: #APP
+; CHECK-NEXT: nop
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: or %s11, 0, %s9
+ %2 = fcmp fast ult float %0, 0.000000e+00
+ br i1 %2, label %4, label %3
+
+3: ; preds = %1
+ tail call void asm sideeffect "nop", ""()
+ br label %4
+
+4: ; preds = %3, %1
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @br_cc_imm_double(double %0) {
+; CHECK-LABEL: br_cc_imm_double:
+; CHECK: .LBB{{[0-9]+}}_4:
+; CHECK-NEXT: brgt.d 0, %s0, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: #APP
+; CHECK-NEXT: nop
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: or %s11, 0, %s9
+ %2 = fcmp fast ult double %0, 0.000000e+00
+ br i1 %2, label %4, label %3
+
+3: ; preds = %1
+ tail call void asm sideeffect "nop", ""()
+ br label %4
+
+4: ; preds = %3, %1
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @br_cc_imm_quad(fp128 %0) {
+; CHECK-LABEL: br_cc_imm_quad:
+; CHECK: .LBB{{[0-9]+}}_4:
+; CHECK-NEXT: lea %s2, .LCPI{{[0-9]+}}_0 at lo
+; CHECK-NEXT: and %s2, %s2, (32)0
+; CHECK-NEXT: lea.sl %s2, .LCPI{{[0-9]+}}_0 at hi(, %s2)
+; CHECK-NEXT: ld %s4, 8(, %s2)
+; CHECK-NEXT: ld %s5, (, %s2)
+; CHECK-NEXT: fcmp.q %s0, %s4, %s0
+; CHECK-NEXT: brlt.d 0, %s0, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: #APP
+; CHECK-NEXT: nop
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: .LBB{{[0-9]+}}_2:
+; CHECK-NEXT: or %s11, 0, %s9
+ %2 = fcmp fast ult fp128 %0, 0xL00000000000000000000000000000000
+ br i1 %2, label %4, label %3
+
+3: ; preds = %1
+ tail call void asm sideeffect "nop", ""()
+ br label %4
+
+4: ; preds = %3, %1
+ ret void
+}
diff --git a/llvm/test/CodeGen/VE/branch1.ll b/llvm/test/CodeGen/VE/branch1.ll
deleted file mode 100644
index a00102aa838c..000000000000
--- a/llvm/test/CodeGen/VE/branch1.ll
+++ /dev/null
@@ -1,300 +0,0 @@
-; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
-
-define signext i8 @func1(i8 signext %a, i8 signext %b) {
-; CHECK-LABEL: func1:
-; CHECK: .LBB{{[0-9]+}}_5:
-; CHECK-NEXT: brle.w %s0, %s1, .LBB{{[0-9]+}}_1
-; CHECK-NEXT: # %bb.2: # %on.true
-; CHECK-NEXT: lea %s0, ret at lo
-; CHECK-NEXT: and %s0, %s0, (32)0
-; CHECK-NEXT: lea.sl %s12, ret at hi(, %s0)
-; CHECK-NEXT: or %s0, 2, (0)1
-; CHECK-NEXT: bsic %s10, (, %s12)
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
-; CHECK-NEXT: br.l.t .LBB{{[0-9]+}}_3
-; CHECK-NEXT: .LBB{{[0-9]+}}_1:
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: .LBB{{[0-9]+}}_3: # %join
-; CHECK-NEXT: sll %s0, %s0, 56
-; CHECK-NEXT: sra.l %s0, %s0, 56
-; CHECK-NEXT: or %s11, 0, %s9
-entry:
- %cmp = icmp sgt i8 %a, %b
- br i1 %cmp, label %on.true, label %join
-
-on.true:
- %ret.val = tail call i32 @ret(i32 2)
- %r8 = trunc i32 %ret.val to i8
- br label %join
-
-join:
- %r = phi i8 [ %r8, %on.true ], [ 0, %entry ]
- ret i8 %r
-}
-
-declare i32 @ret(i32)
-
-define i32 @func2(i16 signext %a, i16 signext %b) {
-; CHECK-LABEL: func2:
-; CHECK: .LBB{{[0-9]+}}_5:
-; CHECK-NEXT: brle.w %s0, %s1, .LBB{{[0-9]+}}_1
-; CHECK-NEXT: # %bb.2: # %on.true
-; CHECK-NEXT: lea %s0, ret at lo
-; CHECK-NEXT: and %s0, %s0, (32)0
-; CHECK-NEXT: lea.sl %s12, ret at hi(, %s0)
-; CHECK-NEXT: or %s0, 2, (0)1
-; CHECK-NEXT: bsic %s10, (, %s12)
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
-; CHECK-NEXT: br.l.t .LBB{{[0-9]+}}_3
-; CHECK-NEXT: .LBB{{[0-9]+}}_1:
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: .LBB{{[0-9]+}}_3: # %join
-; CHECK-NEXT: or %s11, 0, %s9
-entry:
- %cmp = icmp sgt i16 %a, %b
- br i1 %cmp, label %on.true, label %join
-
-on.true:
- %ret.val = tail call i32 @ret(i32 2)
- br label %join
-
-join:
- %r = phi i32 [ %ret.val, %on.true ], [ 0, %entry ]
- ret i32 %r
-}
-
-define i32 @func3(i32 %a, i32 %b) {
-; CHECK-LABEL: func3:
-; CHECK: .LBB{{[0-9]+}}_5:
-; CHECK-NEXT: brle.w %s0, %s1, .LBB{{[0-9]+}}_1
-; CHECK-NEXT: # %bb.2: # %on.true
-; CHECK-NEXT: lea %s0, ret at lo
-; CHECK-NEXT: and %s0, %s0, (32)0
-; CHECK-NEXT: lea.sl %s12, ret at hi(, %s0)
-; CHECK-NEXT: or %s0, 2, (0)1
-; CHECK-NEXT: bsic %s10, (, %s12)
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
-; CHECK-NEXT: br.l.t .LBB{{[0-9]+}}_3
-; CHECK-NEXT: .LBB{{[0-9]+}}_1:
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: .LBB{{[0-9]+}}_3: # %join
-; CHECK-NEXT: or %s11, 0, %s9
-entry:
- %cmp = icmp sgt i32 %a, %b
- br i1 %cmp, label %on.true, label %join
-
-on.true:
- %ret.val = tail call i32 @ret(i32 2)
- br label %join
-
-join:
- %r = phi i32 [ %ret.val, %on.true ], [ 0, %entry ]
- ret i32 %r
-}
-
-define i32 @func4(i64 %a, i64 %b) {
-; CHECK-LABEL: func4:
-; CHECK: .LBB{{[0-9]+}}_5:
-; CHECK-NEXT: brle.l %s0, %s1, .LBB{{[0-9]+}}_1
-; CHECK-NEXT: # %bb.2: # %on.true
-; CHECK-NEXT: lea %s0, ret at lo
-; CHECK-NEXT: and %s0, %s0, (32)0
-; CHECK-NEXT: lea.sl %s12, ret at hi(, %s0)
-; CHECK-NEXT: or %s0, 2, (0)1
-; CHECK-NEXT: bsic %s10, (, %s12)
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
-; CHECK-NEXT: br.l.t .LBB{{[0-9]+}}_3
-; CHECK-NEXT: .LBB{{[0-9]+}}_1:
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: .LBB{{[0-9]+}}_3: # %join
-; CHECK-NEXT: or %s11, 0, %s9
-entry:
- %cmp = icmp sgt i64 %a, %b
- br i1 %cmp, label %on.true, label %join
-
-on.true:
- %ret.val = tail call i32 @ret(i32 2)
- br label %join
-
-join:
- %r = phi i32 [ %ret.val, %on.true ], [ 0, %entry ]
- ret i32 %r
-}
-
-define i32 @func5(i8 zeroext %a, i8 zeroext %b) {
-; CHECK-LABEL: func5:
-; CHECK: .LBB{{[0-9]+}}_5:
-; CHECK-NEXT: cmpu.w %s0, %s1, %s0
-; CHECK-NEXT: brle.w 0, %s0, .LBB{{[0-9]+}}_1
-; CHECK-NEXT: # %bb.2: # %on.true
-; CHECK-NEXT: lea %s0, ret at lo
-; CHECK-NEXT: and %s0, %s0, (32)0
-; CHECK-NEXT: lea.sl %s12, ret at hi(, %s0)
-; CHECK-NEXT: or %s0, 2, (0)1
-; CHECK-NEXT: bsic %s10, (, %s12)
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
-; CHECK-NEXT: br.l.t .LBB{{[0-9]+}}_3
-; CHECK-NEXT: .LBB{{[0-9]+}}_1:
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: .LBB{{[0-9]+}}_3: # %join
-; CHECK-NEXT: or %s11, 0, %s9
-entry:
- %cmp = icmp ugt i8 %a, %b
- br i1 %cmp, label %on.true, label %join
-
-on.true:
- %ret.val = tail call i32 @ret(i32 2)
- br label %join
-
-join:
- %r = phi i32 [ %ret.val, %on.true ], [ 0, %entry ]
- ret i32 %r
-}
-
-define i32 @func6(i16 zeroext %a, i16 zeroext %b) {
-; CHECK-LABEL: func6:
-; CHECK: .LBB{{[0-9]+}}_5:
-; CHECK-NEXT: cmpu.w %s0, %s1, %s0
-; CHECK-NEXT: brle.w 0, %s0, .LBB{{[0-9]+}}_1
-; CHECK-NEXT: # %bb.2: # %on.true
-; CHECK-NEXT: lea %s0, ret at lo
-; CHECK-NEXT: and %s0, %s0, (32)0
-; CHECK-NEXT: lea.sl %s12, ret at hi(, %s0)
-; CHECK-NEXT: or %s0, 2, (0)1
-; CHECK-NEXT: bsic %s10, (, %s12)
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
-; CHECK-NEXT: br.l.t .LBB{{[0-9]+}}_3
-; CHECK-NEXT: .LBB{{[0-9]+}}_1:
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: .LBB{{[0-9]+}}_3: # %join
-; CHECK-NEXT: or %s11, 0, %s9
-entry:
- %cmp = icmp ugt i16 %a, %b
- br i1 %cmp, label %on.true, label %join
-
-on.true:
- %ret.val = tail call i32 @ret(i32 2)
- br label %join
-
-join:
- %r = phi i32 [ %ret.val, %on.true ], [ 0, %entry ]
- ret i32 %r
-}
-
-define i32 @func7(i32 %a, i32 %b) {
-; CHECK-LABEL: func7:
-; CHECK: .LBB{{[0-9]+}}_5:
-; CHECK-NEXT: cmpu.w %s0, %s1, %s0
-; CHECK-NEXT: brle.w 0, %s0, .LBB{{[0-9]+}}_1
-; CHECK-NEXT: # %bb.2: # %on.true
-; CHECK-NEXT: lea %s0, ret at lo
-; CHECK-NEXT: and %s0, %s0, (32)0
-; CHECK-NEXT: lea.sl %s12, ret at hi(, %s0)
-; CHECK-NEXT: or %s0, 2, (0)1
-; CHECK-NEXT: bsic %s10, (, %s12)
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
-; CHECK-NEXT: br.l.t .LBB{{[0-9]+}}_3
-; CHECK-NEXT: .LBB{{[0-9]+}}_1:
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: .LBB{{[0-9]+}}_3: # %join
-; CHECK-NEXT: or %s11, 0, %s9
-entry:
- %cmp = icmp ugt i32 %a, %b
- br i1 %cmp, label %on.true, label %join
-
-on.true:
- %ret.val = tail call i32 @ret(i32 2)
- br label %join
-
-join:
- %r = phi i32 [ %ret.val, %on.true ], [ 0, %entry ]
- ret i32 %r
-}
-
-define i32 @func8(float %a, float %b) {
-; CHECK-LABEL: func8:
-; CHECK: .LBB{{[0-9]+}}_5:
-; CHECK-NEXT: brlenan.s %s0, %s1, .LBB{{[0-9]+}}_1
-; CHECK-NEXT: # %bb.2: # %on.true
-; CHECK-NEXT: lea %s0, ret at lo
-; CHECK-NEXT: and %s0, %s0, (32)0
-; CHECK-NEXT: lea.sl %s12, ret at hi(, %s0)
-; CHECK-NEXT: or %s0, 2, (0)1
-; CHECK-NEXT: bsic %s10, (, %s12)
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
-; CHECK-NEXT: br.l.t .LBB{{[0-9]+}}_3
-; CHECK-NEXT: .LBB{{[0-9]+}}_1:
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: .LBB{{[0-9]+}}_3: # %join
-; CHECK-NEXT: or %s11, 0, %s9
-entry:
- %cmp = fcmp ogt float %a, %b
- br i1 %cmp, label %on.true, label %join
-
-on.true:
- %ret.val = tail call i32 @ret(i32 2)
- br label %join
-
-join:
- %r = phi i32 [ %ret.val, %on.true ], [ 0, %entry ]
- ret i32 %r
-}
-
-define i32 @func9(double %a, double %b) {
-; CHECK-LABEL: func9:
-; CHECK: .LBB{{[0-9]+}}_5:
-; CHECK-NEXT: brlenan.d %s0, %s1, .LBB{{[0-9]+}}_1
-; CHECK-NEXT: # %bb.2: # %on.true
-; CHECK-NEXT: lea %s0, ret at lo
-; CHECK-NEXT: and %s0, %s0, (32)0
-; CHECK-NEXT: lea.sl %s12, ret at hi(, %s0)
-; CHECK-NEXT: or %s0, 2, (0)1
-; CHECK-NEXT: bsic %s10, (, %s12)
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
-; CHECK-NEXT: br.l.t .LBB{{[0-9]+}}_3
-; CHECK-NEXT: .LBB{{[0-9]+}}_1:
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: .LBB{{[0-9]+}}_3: # %join
-; CHECK-NEXT: or %s11, 0, %s9
-entry:
- %cmp = fcmp ogt double %a, %b
- br i1 %cmp, label %on.true, label %join
-
-on.true:
- %ret.val = tail call i32 @ret(i32 2)
- br label %join
-
-join:
- %r = phi i32 [ %ret.val, %on.true ], [ 0, %entry ]
- ret i32 %r
-}
-
-define i32 @func10(double %a, double %b) {
-; CHECK-LABEL: func10:
-; CHECK: .LBB{{[0-9]+}}_5:
-; CHECK-NEXT: lea.sl %s1, 1075052544
-; CHECK-NEXT: brlenan.d %s0, %s1, .LBB{{[0-9]+}}_1
-; CHECK-NEXT: # %bb.2: # %on.true
-; CHECK-NEXT: lea %s0, ret at lo
-; CHECK-NEXT: and %s0, %s0, (32)0
-; CHECK-NEXT: lea.sl %s12, ret at hi(, %s0)
-; CHECK-NEXT: or %s0, 2, (0)1
-; CHECK-NEXT: bsic %s10, (, %s12)
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
-; CHECK-NEXT: br.l.t .LBB{{[0-9]+}}_3
-; CHECK-NEXT: .LBB{{[0-9]+}}_1:
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: .LBB{{[0-9]+}}_3: # %join
-; CHECK-NEXT: or %s11, 0, %s9
-entry:
- %cmp = fcmp ogt double %a, 5.000000e+00
- br i1 %cmp, label %on.true, label %join
-
-on.true:
- %ret.val = tail call i32 @ret(i32 2)
- br label %join
-
-join:
- %r = phi i32 [ %ret.val, %on.true ], [ 0, %entry ]
- ret i32 %r
-}
diff --git a/llvm/test/CodeGen/VE/brcond.ll b/llvm/test/CodeGen/VE/brcond.ll
index 515b6878c3ed..27f19a586b3c 100644
--- a/llvm/test/CodeGen/VE/brcond.ll
+++ b/llvm/test/CodeGen/VE/brcond.ll
@@ -1,8 +1,8 @@
; RUN: llc < %s -mtriple=ve | FileCheck %s
; Function Attrs: nounwind
-define void @test_then(i1 zeroext %0) {
-; CHECK-LABEL: test_then:
+define void @brcond_then(i1 zeroext %0) {
+; CHECK-LABEL: brcond_then:
; CHECK: .LBB{{[0-9]+}}_4:
; CHECK-NEXT: breq.w 0, %s0, .LBB{{[0-9]+}}_2
; CHECK-NEXT: # %bb.1:
@@ -22,8 +22,8 @@ define void @test_then(i1 zeroext %0) {
}
; Function Attrs: nounwind
-define void @test_else(i1 zeroext %0) {
-; CHECK-LABEL: test_else:
+define void @brcond_else(i1 zeroext %0) {
+; CHECK-LABEL: brcond_else:
; CHECK: .LBB{{[0-9]+}}_4:
; CHECK-NEXT: brne.w 0, %s0, .LBB{{[0-9]+}}_2
; CHECK-NEXT: # %bb.1:
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