[llvm] 354d310 - [PowerPC] Skip combining (uint_to_fp x) if x is not simple type
Kai Luo via llvm-commits
llvm-commits at lists.llvm.org
Sun Oct 18 22:23:53 PDT 2020
Author: Kai Luo
Date: 2020-10-19T05:23:46Z
New Revision: 354d3106c6a9d6de824ee7ffa501387592b15afa
URL: https://github.com/llvm/llvm-project/commit/354d3106c6a9d6de824ee7ffa501387592b15afa
DIFF: https://github.com/llvm/llvm-project/commit/354d3106c6a9d6de824ee7ffa501387592b15afa.diff
LOG: [PowerPC] Skip combining (uint_to_fp x) if x is not simple type
Current powerpc64le backend hits
```
Combining: t7: f64 = uint_to_fp t6
llc: llvm-project/llvm/include/llvm/CodeGen/ValueTypes.h:291: llvm::MVT llvm::EVT::getSimpleVT() const: Assertion `isSimple() && "Expected a SimpleValueType!"' failed.
```
This patch fixes it by skipping combination if `t6` is not simple type.
Fixed https://bugs.llvm.org/show_bug.cgi?id=47660.
Reviewed By: #powerpc, steven.zhang
Differential Revision: https://reviews.llvm.org/D88388
Added:
llvm/test/CodeGen/PowerPC/pr47660.ll
Modified:
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index d9b9689a8a0e..3b32d0b84750 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -14075,6 +14075,8 @@ SDValue PPCTargetLowering::combineFPToIntToFP(SDNode *N,
// from the hardware.
if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
return SDValue();
+ if (!Op.getOperand(0).getValueType().isSimple())
+ return SDValue();
if (Op.getOperand(0).getValueType().getSimpleVT() <= MVT(MVT::i1) ||
Op.getOperand(0).getValueType().getSimpleVT() > MVT(MVT::i64))
return SDValue();
diff --git a/llvm/test/CodeGen/PowerPC/pr47660.ll b/llvm/test/CodeGen/PowerPC/pr47660.ll
new file mode 100644
index 000000000000..64feb2735806
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/pr47660.ll
@@ -0,0 +1,45 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -ppc-asm-full-reg-names -verify-machineinstrs \
+; RUN: -mtriple=powerpc64le-linux-gnu < %s | FileCheck \
+; RUN: -check-prefix=CHECK-LE %s
+; RUN: llc -ppc-asm-full-reg-names -verify-machineinstrs \
+; RUN: -mtriple=powerpc64-linux-gnu < %s | FileCheck \
+; RUN: -check-prefix=CHECK-BE %s
+
+define dso_local i24 @_Z1f1c(i24 %g.coerce) local_unnamed_addr #0 {
+; CHECK-LE-LABEL: _Z1f1c:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: clrlwi r3, r3, 24
+; CHECK-LE-NEXT: xxlxor f1, f1, f1
+; CHECK-LE-NEXT: mtfprwz f0, r3
+; CHECK-LE-NEXT: xscvuxddp f0, f0
+; CHECK-LE-NEXT: xsmuldp f0, f0, f1
+; CHECK-LE-NEXT: xscvdpsxws f0, f0
+; CHECK-LE-NEXT: mffprwz r3, f0
+; CHECK-LE-NEXT: clrldi r3, r3, 32
+; CHECK-LE-NEXT: blr
+;
+; CHECK-BE-LABEL: _Z1f1c:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: clrldi r3, r3, 56
+; CHECK-BE-NEXT: std r3, -16(r1)
+; CHECK-BE-NEXT: addis r3, r2, .LCPI0_0 at toc@ha
+; CHECK-BE-NEXT: lfd f0, -16(r1)
+; CHECK-BE-NEXT: lfs f1, .LCPI0_0 at toc@l(r3)
+; CHECK-BE-NEXT: fcfid f0, f0
+; CHECK-BE-NEXT: fmul f0, f0, f1
+; CHECK-BE-NEXT: fctiwz f0, f0
+; CHECK-BE-NEXT: stfd f0, -8(r1)
+; CHECK-BE-NEXT: lwz r3, -4(r1)
+; CHECK-BE-NEXT: clrldi r3, r3, 32
+; CHECK-BE-NEXT: blr
+entry:
+ %0 = and i24 %g.coerce, 255
+ %conv1 = uitofp i24 %0 to double
+ %mul = fmul double 0.000000e+00, %conv1
+ %conv2 = fptoui double %mul to i8
+ %retval.sroa.0.0.insert.ext = zext i8 %conv2 to i24
+ ret i24 %retval.sroa.0.0.insert.ext
+}
+
+attributes #0 = { "use-soft-float"="false" }
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