[PATCH] D89665: [LSR] ignore profitable chain optimization when instruction number is the major cost

[ChenZheng via Phabricator via llvm-commits]

shchenz created this revision.
shchenz added reviewers: hfinkel, qcolombet, samparker, PowerPC.
Herald added subscribers: llvm-commits, steven.zhang, pengfei, hiraditya, nemanjai.
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shchenz requested review of this revision.

`isProfitableChain` was added based on register number cost. But now, there are some targets like X86/PowerPC taking instruction number as the major cost.

So on these targets, `isProfitableChain` wrongly eliminates some LSRUse based on register number when collecting chains/LSRUses, these eliminated LSRUse may impact the instruction number a lot in later rate cost phase. Thus we will get a suboptimal loop code sequence.

Maybe we need to add a new hook if target overrides `isLSRCostLess` and sets instruction number as the first priority of the cost?

This patch can make some cpu2017 benchmarks improve on PowerPC.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D89665

Files:
  llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
  llvm/test/CodeGen/PowerPC/lsr-profitable-chain.ll

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