[PATCH] D89575: Change target for sched-aliases.td test case

[Eugene Leviant via Phabricator via llvm-commits]

evgeny777 created this revision.
evgeny777 added a reviewer: Paul-C-Anagnostopoulos.
Herald added a project: LLVM.
evgeny777 requested review of this revision.

See discussion in D89114 <https://reviews.llvm.org/D89114>


https://reviews.llvm.org/D89575

Files:
  llvm/test/TableGen/sched-aliases.td


Index: llvm/test/TableGen/sched-aliases.td
===================================================================
--- llvm/test/TableGen/sched-aliases.td
+++ llvm/test/TableGen/sched-aliases.td
@@ -1,26 +1,30 @@
 // REQUIRES: asserts
-// REQUIRES: aarch64-registered-target
-// RUN: llvm-tblgen -gen-instr-info %s -I%p/../../include -I%p/../../lib/Target/AArch64 -o %t -debug-only=subtarget-emitter 2>&1 | FileCheck %s 
+// REQUIRES: arm-registered-target
+// RUN: llvm-tblgen -gen-instr-info %s -I%p/../../include -I%p/../../lib/Target/ARM -o %t -debug-only=subtarget-emitter 2>&1 | FileCheck %s
 
-// Check that we've defined scheduling classes for FMOVv2f32_ns and FMOVv2f64 for Model0
-// CHECK: InstRW: New SC [[SC:[0-9]+]]:FMOVv2f32_ns on Model0
-// CHECK: InstRW: New SC [[SC2:[0-9]+]]:FMOVv2f64_ns on Model0
+// Check that we've defined scheduling classes for VMOVRRS and FMOVv2f64 for Model0
+// CHECK: InstRW: New SC [[SC:[0-9]+]]:VMOVRRS on Model0
+// CHECK: InstRW: Reuse SC [[SC2:[0-9]+]]:VMOVRS on Model0
 
-// Generic transition for WriteV should be defined for Model0 as well as for
+// Generic transition for WriteFPMOV should be defined for Model0 as well as for
 // all instructions without explicitly defined scheduling classes.
-// CHECK: Adding transition from WriteV({{[0-9]+}}) to Model0WriteV_4cyc({{[0-9]+}}) on processor indices
-// CHECK: Adding transition from WriteV({{[0-9]+}}) to Model0WriteV_2cyc({{[0-9]+}}) on processor indices
+// CHECK: Adding transition from {{.*}}WriteFPMOV({{[0-9]+}}) to Model0WriteFPMOV_4cyc({{[0-9]+}}) on processor indices
+// CHECK: Adding transition from {{.*}}WriteFPMOV({{[0-9]+}}) to Model0WriteFPMOV_2cyc({{[0-9]+}}) on processor indices
 
-// Transition from FMOVv2f64_ns should still be added for Model0,
+// Transition from VMOVRS should still be added for Model0,
 // even though we've defined custom scheduling class.
-// CHECK: Adding transition from FMOVv2f64_ns([[SC2]]) to Model0WriteV_4cyc({{[0-9]+}}) on processor indices
-// CHECK-NEXT: Adding transition from FMOVv2f64_ns([[SC2]]) to Model0WriteV_2cyc({{[0-9]+}}) on processor indices
+// CHECK: Adding transition from VMOVRS([[SC2]]) to Model0WriteFPMOV_4cyc({{[0-9]+}}) on processor indices
+// CHECK-NEXT: Adding transition from VMOVRS([[SC2]]) to Model0WriteFPMOV_2cyc({{[0-9]+}}) on processor indices
 
-// Transition from FMOVv2f32_ns should not be added for Model0,
+// Transition from VMOVRRS should not be added for Model0,
 // because custom sched class for it is defined and it's not variant.
-// CHECK-NOT: Adding transition from FMOVv2f32_ns([[SC]])
+// CHECK-NOT: Adding transition from VMOVRRS([[SC]])
 
-include "AArch64.td"
+include "ARM.td"
+
+let FunctionMapper = "ARM_AM::getSORegShOp" in {
+  def CheckShiftNone                : CheckImmOperand_s<3, "ARM_AM::no_shift">;
+}
 
 def Model0 : SchedMachineModel {
   let CompleteModel = 0;
@@ -30,19 +34,19 @@
 
 let SchedModel = Model0 in {
 
-def Model0WriteV_4cyc : SchedWriteRes<[Model0UnitV]> { let Latency = 4; }
-def Model0WriteV_2cyc : SchedWriteRes<[Model0UnitV]> { let Latency = 2; }
-def Model0WriteV_1cyc : SchedWriteRes<[Model0UnitV]> { let Latency = 1; }
+def Model0WriteFPMOV_4cyc : SchedWriteRes<[Model0UnitV]> { let Latency = 4; }
+def Model0WriteFPMOV_2cyc : SchedWriteRes<[Model0UnitV]> { let Latency = 2; }
+def Model0WriteFPMOV_1cyc : SchedWriteRes<[Model0UnitV]> { let Latency = 1; }
 
-def Model0QFormPred : MCSchedPredicate<CheckQForm>;
-def Model0WriteV : SchedWriteVariant<[
-       SchedVar<Model0QFormPred, [Model0WriteV_4cyc]>,
-       SchedVar<NoSchedPred, [Model0WriteV_2cyc]>]>;
+def Model0QFormPred : MCSchedPredicate<CheckShiftNone>;
+def Model0WriteFPMOV : SchedWriteVariant<[
+       SchedVar<Model0QFormPred, [Model0WriteFPMOV_4cyc]>,
+       SchedVar<NoSchedPred, [Model0WriteFPMOV_2cyc]>]>;
 
-def : SchedAlias<WriteV, Model0WriteV>;
+def : SchedAlias<WriteFPMOV, Model0WriteFPMOV>;
 
-def : InstRW<[Model0WriteV_1cyc], (instrs FMOVv2f32_ns)>;
-def : InstRW<[WriteV], (instrs FMOVv2f64_ns)>;
+def : InstRW<[Model0WriteFPMOV_1cyc], (instrs VMOVRRS)>;
+def : InstRW<[WriteFPMOV], (instrs VMOVRS)>;
 }
 
 def : ProcessorModel<"foo-0-model", Model0, []>;


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