[PATCH] D89114: [TableGen][SchedModels] Fix aliasing of SchedWriteVariant

[Eugene Leviant via Phabricator via llvm-commits]

evgeny777 added a comment.

> I do wish there was a faster way to test what you're testing.

Switching to ARM target (instead of AArch64) makes it twice faster. I can submit a patch for review if you like.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D89114/new/

https://reviews.llvm.org/D89114