[llvm] fe8281e - [InstCombine] visitAnd - add some ((val OP C1) & C2) vector test coverage

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2020-10-16T15:43:11+01:00
New Revision: fe8281e2d009d9ab0b89cad2cb56defceb7fa9b1

URL: https://github.com/llvm/llvm-project/commit/fe8281e2d009d9ab0b89cad2cb56defceb7fa9b1
DIFF: https://github.com/llvm/llvm-project/commit/fe8281e2d009d9ab0b89cad2cb56defceb7fa9b1.diff

LOG: [InstCombine] visitAnd - add some ((val OP C1) & C2) vector test coverage

Added: 
    

Modified: 
    llvm/test/Transforms/InstCombine/add.ll
    llvm/test/Transforms/InstCombine/and.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/Transforms/InstCombine/add.ll b/llvm/test/Transforms/InstCombine/add.ll
index 282d819e46dd..e8f696a54557 100644
--- a/llvm/test/Transforms/InstCombine/add.ll
+++ b/llvm/test/Transforms/InstCombine/add.ll
@@ -348,6 +348,39 @@ define i8 @test16(i8 %A) {
   ret i8 %C
 }
 
+define <2 x i8> @test16_uniform(<2 x i8> %A) {
+; CHECK-LABEL: @test16_uniform(
+; CHECK-NEXT:    [[B:%.*]] = add <2 x i8> [[A:%.*]], <i8 16, i8 16>
+; CHECK-NEXT:    [[C:%.*]] = and <2 x i8> [[B]], <i8 16, i8 16>
+; CHECK-NEXT:    ret <2 x i8> [[C]]
+;
+  %B = add <2 x i8> %A, <i8 16, i8 16>
+  %C = and <2 x i8> %B, <i8 16, i8 16>
+  ret <2 x i8> %C
+}
+
+define <2 x i8> @test16_undef(<2 x i8> %A) {
+; CHECK-LABEL: @test16_undef(
+; CHECK-NEXT:    [[B:%.*]] = add <2 x i8> [[A:%.*]], <i8 16, i8 undef>
+; CHECK-NEXT:    [[C:%.*]] = and <2 x i8> [[B]], <i8 16, i8 undef>
+; CHECK-NEXT:    ret <2 x i8> [[C]]
+;
+  %B = add <2 x i8> %A, <i8 16, i8 undef>
+  %C = and <2 x i8> %B, <i8 16, i8 undef>
+  ret <2 x i8> %C
+}
+
+define <2 x i8> @test16_nonuniform(<2 x i8> %A) {
+; CHECK-LABEL: @test16_nonuniform(
+; CHECK-NEXT:    [[B:%.*]] = add <2 x i8> [[A:%.*]], <i8 16, i8 4>
+; CHECK-NEXT:    [[C:%.*]] = and <2 x i8> [[B]], <i8 16, i8 4>
+; CHECK-NEXT:    ret <2 x i8> [[C]]
+;
+  %B = add <2 x i8> %A, <i8 16, i8 4>
+  %C = and <2 x i8> %B, <i8 16, i8 4>
+  ret <2 x i8> %C
+}
+
 define i32 @test17(i32 %A) {
 ; CHECK-LABEL: @test17(
 ; CHECK-NEXT:    [[C:%.*]] = sub i32 0, [[A:%.*]]

diff  --git a/llvm/test/Transforms/InstCombine/and.ll b/llvm/test/Transforms/InstCombine/and.ll
index 13ce3b87d285..4c6d7fa6e48b 100644
--- a/llvm/test/Transforms/InstCombine/and.ll
+++ b/llvm/test/Transforms/InstCombine/and.ll
@@ -479,6 +479,19 @@ define i64 @test35(i32 %X) {
   ret i64 %res
 }
 
+define <2 x i64> @test35_uniform(<2 x i32> %X) {
+; CHECK-LABEL: @test35_uniform(
+; CHECK-NEXT:    [[ZEXT:%.*]] = zext <2 x i32> [[X:%.*]] to <2 x i64>
+; CHECK-NEXT:    [[ZSUB:%.*]] = sub nsw <2 x i64> zeroinitializer, [[ZEXT]]
+; CHECK-NEXT:    [[RES:%.*]] = and <2 x i64> [[ZSUB]], <i64 240, i64 240>
+; CHECK-NEXT:    ret <2 x i64> [[RES]]
+;
+  %zext = zext <2 x i32> %X to <2 x i64>
+  %zsub = sub <2 x i64> zeroinitializer, %zext
+  %res = and <2 x i64> %zsub, <i64 240, i64 240>
+  ret <2 x i64> %res
+}
+
 define i64 @test36(i32 %X) {
 ; CHECK-LABEL: @test36(
 ; CHECK-NEXT:    [[TMP1:%.*]] = add i32 [[X:%.*]], 7
@@ -492,6 +505,19 @@ define i64 @test36(i32 %X) {
   ret i64 %res
 }
 
+define <2 x i64> @test36_undef(<2 x i32> %X) {
+; CHECK-LABEL: @test36_undef(
+; CHECK-NEXT:    [[ZEXT:%.*]] = zext <2 x i32> [[X:%.*]] to <2 x i64>
+; CHECK-NEXT:    [[ZSUB:%.*]] = add <2 x i64> [[ZEXT]], <i64 7, i64 undef>
+; CHECK-NEXT:    [[RES:%.*]] = and <2 x i64> [[ZSUB]], <i64 240, i64 undef>
+; CHECK-NEXT:    ret <2 x i64> [[RES]]
+;
+  %zext = zext <2 x i32> %X to <2 x i64>
+  %zsub = add <2 x i64> %zext, <i64 7, i64 undef>
+  %res = and <2 x i64> %zsub, <i64 240, i64 undef>
+  ret <2 x i64> %res
+}
+
 define i64 @test37(i32 %X) {
 ; CHECK-LABEL: @test37(
 ; CHECK-NEXT:    [[TMP1:%.*]] = mul i32 [[X:%.*]], 7
@@ -505,6 +531,19 @@ define i64 @test37(i32 %X) {
   ret i64 %res
 }
 
+define <2 x i64> @test37_nonuniform(<2 x i32> %X) {
+; CHECK-LABEL: @test37_nonuniform(
+; CHECK-NEXT:    [[ZEXT:%.*]] = zext <2 x i32> [[X:%.*]] to <2 x i64>
+; CHECK-NEXT:    [[ZSUB:%.*]] = mul nuw nsw <2 x i64> [[ZEXT]], <i64 7, i64 9>
+; CHECK-NEXT:    [[RES:%.*]] = and <2 x i64> [[ZSUB]], <i64 240, i64 110>
+; CHECK-NEXT:    ret <2 x i64> [[RES]]
+;
+  %zext = zext <2 x i32> %X to <2 x i64>
+  %zsub = mul <2 x i64> %zext, <i64 7, i64 9>
+  %res = and <2 x i64> %zsub, <i64 240, i64 110>
+  ret <2 x i64> %res
+}
+
 define i64 @test38(i32 %X) {
 ; CHECK-LABEL: @test38(
 ; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[X:%.*]], 240