[PATCH] D88572: AMDGPU/SelectionDAG Check for NaN, DX10Clamp and IEEE in fmed3 combine

[Petar Avramovic via Phabricator via llvm-commits]

Petar.Avramovic updated this revision to Diff 298622.
Petar.Avramovic added a comment.

Respect description of ISD::FMAXNUM and ISD::FMAXNUM_IEEE (their behavior is not affected by IEEE mode).
Legalizer will deal with use of FMAXNUM when IEEE=true (makes sure that potential SNaN input gets quieted) and we can try to fold FMAXNUM_IEEE later.
Most of the test changes come from clamp/fmed on top of fcanonicalize with IEEE=true.

We should probably check if ISD::FMAX... matches IEEE mode when folding min3 and max3 since these also depend on IEEE mode.
However this brings many regressions. For some reason in combine round after legalization nodes are not visited starting from end of the function but kind of random.For example in `min(max(max(.., ..), 0.0) 1.0)` middle max gets visited first and it folds into max3 and we miss clamp fold since min was not visited first.

All of this could be fixed with some test changes.
Currently, there no clean way to represent ISD::FMAXNUM_IEEE in IR. It can only be legalized from ISD::FMAXNUM by quieting its input.
I assume that producer of function with IEEE=true would desire `llvm.maxnum_ieee.*` (TODO introduce this in IR) instead of `llvm.maxnum.*` for IR floating point max.
This would make intention of tests that make use of isKnownNeverSNaN more clear since currently ISD::FMAXNUM_IEEE can't have SNaN input because it can only be produced from ISD::FMAXNUM.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D88572/new/

https://reviews.llvm.org/D88572

Files:
  llvm/lib/Target/AMDGPU/SIISelLowering.cpp
  llvm/test/CodeGen/AMDGPU/clamp-modifier.ll
  llvm/test/CodeGen/AMDGPU/clamp.ll
  llvm/test/CodeGen/AMDGPU/known-never-snan.ll

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